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参数资料
| 型号： | AD9887AKSZ-140 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 30/52页 |
| 文件大小： | 0K |
| 描述： | IC INTRFACE ANALOG/DVI 160-MQFP |
| 标准包装： | 24 |
| 应用： | 图形卡，VGA 接口 |
| 接口： | 模拟和数字 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 封装/外壳： | 160-BQFP |
| 供应商设备封装： | 160-MQFP（28x28） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
| 产品目录页面： | 788 (CN2011-ZH PDF) |
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AD9887A
Rev. B | Page 36 of 52
0x03 4–2
CURRENT Charge-Pump Current
Three bits that establish the current driving the loop
filter in the clock generator.
Table 11. Charge-Pump Currents
CURRENT
Current (μA)
000
50
001
100
010
150
011
250
100
350
101
500
110
750
111
1500
See Table 7 for the recommended CURRENT settings.
The power-up default value is CURRENT = 001.
0x04 7:3
Clock Phase Adjust
A 5-bit value that adjusts the sampling phase in 32 steps
across one pixel period. Each step represents an 11.2°
shift in sampling phase.
The power-up default value is 16.
Clamp Timing
0x05 7:0
Clamp Placement
An 8-bit register that sets the position of the internally
generated clamp.
When EXTCLMP = 0, a clamp signal is generated
internally at a position established by the clamp
placement for a duration set by the clamp duration.
Clamping is started [clamp placement] pixel periods
after the trailing edge of Hsync. The clamp placement
can be programmed to any value between 1 and 255.
A value of 0 is not supported.
The clamp should be placed during a time when the
input signal presents a stable black-level reference,
usually during a period between Hsync and the image
called the back porch. When EXTCLMP = 1, this
register is ignored.
0x06 7:0
Clamp Duration
An 8-bit register that sets the duration of the internally
generated clamp.
When EXTCLMP = 0, a clamp signal is generated
internally at a position established by the clamp
placement for a duration set by the clamp duration.
Clamping is started [clamp placement] pixel periods
after the trailing edge of Hsync and continues for [clamp
duration] pixel periods. The clamp duration can be
programmed to a value between 1 and 255. A value of 0
is not supported.
For the best results, the clamp duration should be set to
include the majority of the black reference signal time
that follows the Hsync signal trailing edge. Insufficient
clamping time can produce brightness changes at the top
of the screen and can cause slow recovery from large
changes in the average picture level (APL) or brightness.
When EXTCLMP = 1, this register is ignored.
Hsync Pulse Width
0x07 7:0
Hsync Output Pulse Width
An 8-bit register that sets the duration of the Hsync
output pulse.
The leading edge of the Hsync output is triggered by the
internally generated, phase-adjusted PLL feedback clock.
The AD9887A counts the number of pixel clock cycles
set in this register. This triggers the trailing edge of the
Hsync output, which is also phase adjusted.
Input Gain
0x08 7:0
Red Channel Gain Adjust (REDGAIN)
An 8-bit word that sets the gain of the red channel.
The AD9887A can accommodate input signals with a
full-scale range between 0.5 V and 1.5 V p-p. Setting
REDGAIN to 255 corresponds to an input range of
1.0 V. A REDGAIN of 0 establishes an input range of
0.5 V. Note that increasing REDGAIN results in the
picture having less contrast because the input signal uses
fewer of the available converter codes (see Figure 6).
0x09 7:0
Green Channel Gain Adjust (GREENGAIN)
An 8-bit word that sets the gain of the green channel. See
REDGAIN (0x08).
0x0A 7:0
Blue Channel Gain Adjust (BLUEGAIN)
An 8-bit word that sets the gain of the blue channel. See
REDGAIN (0x08).
Input Offset
0x0B 7:1
Red Channel Offset Adjust (REDOFST)
A 7-bit offset binary word that sets the dc offset of the
red channel (REDOFST). An offset adjustment of 1 LSB
equals approximately 1 LSB change in the ADC offset.
Therefore, the absolute magnitude of the offset adjustment
scales as the gain of the channel changes. A nominal setting
of 63 results in the channel nominally clamping to Code 00
during the back porch clamping interval. An offset setting
of 127 results in the channel clamping to Code 63 of the
ADC. An offset setting of 0 clamps to Code 63 (off the
bottom of the range). Increasing the value of red offset
decreases the brightness of the channel.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9887AKSZ-1401 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887AKSZ-170 | 功能描述:IC INTRFACE ANALOG/DVI 160-MQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD9887AKSZ-170 | 制造商:Analog Devices 功能描述:IC DUAL DISPLAY INTERFACE |
| AD9887AKSZ-1701 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887APCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
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