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| 型号： | AD9887AKSZ-140 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 29/52页 |
| 文件大小： | 0K |
| 描述： | IC INTRFACE ANALOG/DVI 160-MQFP |
| 标准包装： | 24 |
| 应用： | 图形卡，VGA 接口 |
| 接口： | 模拟和数字 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 封装/外壳： | 160-BQFP |
| 供应商设备封装： | 160-MQFP（28x28） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
| 产品目录页面： | 788 (CN2011-ZH PDF) |
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AD9887A
Rev. B | Page 35 of 52
Address
Read and
Write, or
Read Only
Bits
Default
Value
Register Name
Description
0x22
R/W
7:0
00000000
Must be set to default.
0x23
R/W
7:0
00000000
Must be set to 0x2A for proper operation.
0x24
R/W
7:0
00000000
Must be set to default.
0x25
R/W
7:0
11110000
Must be set to default.
0x26
R/W
7:0
11111111
Must be set to default.
0x27
00001111
Must be set to default
1 The AD9887A only updates the PLL divide ratio when the LSBs are written to Register 0x02.
2-WIRE SERIAL CONTROL REGISTER DETAILS
Chip Identification
0x00 7:0
Chip Revision
Bit 7 through Bit 4 represent functional revisions to the
analog interface. Changes in these bits generally indicate
that software and/or hardware changes are required for
the chip to work properly. Bit 3 through Bit 0 represent
nonfunctional related revisions and are reset to 0000
when the MSBs are changed. Changes in these bits are
considered transparent to the user.
PLL Divider Control
0x01 7:0
PLL Divide Ratio MSBs
The 8 MSBs of the 12-bit PLL divide ratio PLLDIV. (The
operational divide ratio is PLLDIV + 1.)
The PLL derives a pixel clock from the incoming Hsync
signal. The pixel clock frequency is then divided by an
integer value, such that the output is phase-locked to
Hsync. This PLLDIV value determines the number of
pixel times (pixels plus horizontal blanking overhead)
per line. This is typically 20% to 30% more than the
number of active pixels in the display.
The 12-bit value of the PLL divider supports divide ratios
from 221 to 4095. The higher the value loaded in this
register, the higher the resulting clock frequency with
respect to a fixed Hsync frequency. VESA has established
standard timing specifications that help determine the value
for PLLDIV as a function of horizontal and vertical display
resolution and frame rate (Table 7). However, many com-
puter systems do not conform precisely to the recom-
mendations, and these numbers should be used only as a
guide. The display system manufacturer should provide
automatic or manual means for optimizing PLLDIV. An
incorrectly set PLLDIV usually produces one or more
vertical noise bars on the display. The greater the error, the
greater the number of bars produced. The power-up default
of PLLDIV is 1693 (PLLDIVM = 0x69, PLLDIVL = 0xDx).
The AD9887A updates the full divide ratio only when
the LSBs are changed. Writing to this register by itself
does not trigger an update.
0x02 7:4
PLL Divide Ratio LSBs
The 4 LSBs of the 12-bit PLL divide ratio PLLDIV. The
operational divide ratio is PLLDIV + 1.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 0x69, PLLDIVL = 0xDx).
The AD9887A updates the full divide ratio only when
the user writes to this register.
Clock Generator Controls
0x03 7
Test
Must be set to 1 for proper device operation.
0x03 6:5
VCO Range Select
Two bits that establish the operating range of the clock
generator.
VCORNGE must be set to correspond with the desired
operating frequency (incoming pixel rate).
The PLL provides the best jitter performance at high
frequencies. To output low pixel rates while minimizing
jitter, the PLL operates at a higher frequency and divides
down the clock rate afterwards. Table 10 shows the pixel
rates for each VCO range setting. The PLL output divisor
is automatically selected with the VCO range setting.
Table 10. VCO Ranges
VCORNGE
Pixel Rate Range
00
12 to 37
01
37 to 74
10
74 to 140
11
140 to 170
The power-up default value is 01.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9887AKSZ-1401 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887AKSZ-170 | 功能描述:IC INTRFACE ANALOG/DVI 160-MQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD9887AKSZ-170 | 制造商:Analog Devices 功能描述:IC DUAL DISPLAY INTERFACE |
| AD9887AKSZ-1701 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Interface for Flat Panel Display |
| AD9887APCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
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