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参数资料
| 型号： | ADSP-21363KSWZ-1AA |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/60页 |
| 文件大小： | 0K |
| 描述： | IC DSP 32BIT 333MHZ EPAD 144LQFP |
| 产品培训模块： | SHARC Processor Overview |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | DAI，SPI |
| 时钟速率： | 333MHz |
| 非易失内存： | ROM（512 kB） |
| 芯片上RAM： | 384kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.20V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LQFP 裸露焊盘 |
| 供应商设备封装： | 144-LQFP（20x20） |
| 包装： | 托盘 |
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
PACKAGE INFORMATION
The information presented in Figure 4 provides details about
the package branding for the ADSP-2136x processor. For a
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Table 8. Absolute Maximum Ratings
Parameter
Rating
a
ADSP-2136x
tppZ-cc
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S
Internal (Core) Supply Voltage (V DDINT )
Analog (PLL) Supply Voltage (A VDD )
External (I/O) Supply Voltage (V DDEXT )
Input Voltage
Output Voltage Swing
Load Capacitance
Storage Temperature Range
Junction Temperature While Biased
–0.3 V to +1.5 V
–0.3 V to +1.5 V
–0.3 V to +4.6 V
–0.5 V to +3.8 V
–0.5 V to V DDEXT + 0.5 V
200 pF
–65°C to +150°C
125°C
Figure 4. Typical Package Brand
Table 7. Package Brand Information
TIMING SPECIFICATIONS
Use the exact timing information given. Do not attempt to
Brand Key
t
pp
Z
cc
vvvvvv.x
n.n
#
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ESD CAUTION
Field Description
Temperature Range
Package Type
RoHS Compliant Designation
See Ordering Guide
Assembly Lot Code
Silicon Revision
RoHS Compliant Designation
Date Code
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. For
voltage reference levels, see Figure 39 on Page 46 under Test
Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
MAXIMUM POWER DISSIPATION
See the Engineer-to-Engineer Note “Estimating Power for the
ADSP-21362 SHARC Processors ” (EE-277) for detailed thermal
and power information regarding maximum power dissipation.
For information on package thermal specifications, see Thermal
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 8 may cause perma-
nent damage to the device. These are stress ratings only;
functional operation of the device at these or any other condi-
tions greater than those indicated in the operational sections of
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Core Clock Requirements
The processor’s internal clock (a multiple of CLKIN) provides
the clock signal for timing internal memory, processor core, and
serial ports. During reset, program the ratio between the proces-
sor’s internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG1–0 pins.
The processor’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL,
see Figure 5 ). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the processor’s
internal clock.
Voltage Controlled Oscillator
In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
Rev. J |
Page 16 of 60 |
July 2013
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相关代理商/技术参数 |
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|---|---|
| ADSP-21363SBBC-ENG | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SBBCZENG | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SBSQ-ENG | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SBSQZENG | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SCSQ-ENG | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
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