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参数资料
| 型号： | ADSP-21363KSWZ-1AA |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/60页 |
| 文件大小： | 0K |
| 描述： | IC DSP 32BIT 333MHZ EPAD 144LQFP |
| 产品培训模块： | SHARC Processor Overview |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | DAI，SPI |
| 时钟速率： | 333MHz |
| 非易失内存： | ROM（512 kB） |
| 芯片上RAM： | 384kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.20V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LQFP 裸露焊盘 |
| 供应商设备封装： | 144-LQFP（20x20） |
| 包装： | 托盘 |
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Power-Up Sequencing
The timing requirements for processor startup are given in
supply comes up after V DDEXT , a leakage current of the order of
three-state leakage current pull-up, pull-down, may be observed
on any pin, even if that is an input only (for example the RESET
pin) until the V DDINT rail has powered up.
Table 10. Power-Up Sequencing Timing Requirements (Processor Startup)
Parameter
Min
Max
Unit
Timing Requirements
t RSTVDD
RESET Low Before V DDINT /V DDEXT On
0
ns
t IVDDEVDD
t CLKVDD 1
t CLKRST
t PLLRST
V DDINT On Before V DDEXT
CLKIN Valid After V DDINT /V DDEXT Valid
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
–50
0
10 2
20
+200
200
ms
ms
μs
μs
Switching Characteristic
t CORERST
Core Reset Deasserted After RESET Deasserted
4096t CK + 2 t CCLK 3, 4
1
2
3
4
Valid V DDINT /V DDEXT assumes that the supplies are fully ramped to their 1.2 V rails and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds,
depending on the design of the power supply subsystem.
Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time.
Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low to properly initialize and propagate
default states at all I/O pins.
The 4096 cycle count depends on t SRST specification in Table 12 . If setup time is not met, 1 additional CLKIN cycle can be added to the core reset time, resulting in 4097 cycles
maximum.
t RSTVDD
RESET
V DDINT
V DDEXT
t IVDDEVDD
t CLKVDD
CLKIN
t CLKRST
CLK_CFG1–0
RESETOUT
t PLLRST
Figure 6. Power-Up Sequencing
t CORERST
Rev. J |
Page 18 of 60 |
July 2013
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相关代理商/技术参数 |
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|---|---|
| ADSP-21363SBBC-ENG | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SBBCZENG | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SBSQ-ENG | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SBSQZENG | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
| ADSP-21363SCSQ-ENG | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
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