参数资料
型号: ADSP-21363KSWZ-1AA
厂商: Analog Devices Inc
文件页数: 42/60页
文件大小: 0K
描述: IC DSP 32BIT 333MHZ EPAD 144LQFP
产品培训模块: SHARC Processor Overview
标准包装: 1
系列: SHARC®
类型: 浮点
接口: DAI,SPI
时钟速率: 333MHz
非易失内存: ROM(512 kB)
芯片上RAM: 384kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 144-LQFP 裸露焊盘
供应商设备封装: 144-LQFP(20x20)
包装: 托盘
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SPI Interface—Master
The processor contains two SPI ports. The primary has dedi-
cated pins and the secondary is available through the DAI. The
timing provided in Table 39 and Table 40 applies to both ports.
Table 39. SPI Interface Protocol—Master Switching and Timing Specifications
K and B Grade
Y Grade
Parameter
Min Max
Min
Max
Unit
Timing Requirements
t SSPIDM
t SSPIDM
t HSPIDM
Data Input Valid to SPICLK Edge (Data Input Setup Time)
Data Input Valid to SPICLK Edge (Data Input Setup Time) (SPI2)
SPICLK Last Sampling Edge to Data Input Not Valid
5.2
8.2
2
6.2
9.5
2
ns
ns
ns
Switching Characteristics
t SPICLKM
t SPICHM
t SPICLM
t DDSPIDM
t DDSPIDM
t HDSPIDM
t SDSCIM
t SDSCIM
t HDSM
t SPITDM
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Valid (Data Out Delay Time) (SPI2)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge
FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge (SPI2)
Last SPICLK Edge to FLAG3–0IN High
Sequential Transfer Delay
8 × t PCLK – 2
4 × t PCLK – 2
4 × t PCLK – 2
4 × t PCLK – 2
4 × t PCLK – 2.5
4 × t PCLK – 2.5
4 × t PCLK – 2
4 × t PCLK – 1
3.0
8.0
8 × t PCLK – 2
4 × t PCLK – 2
4 × t PCLK – 2
4 × t PCLK – 2
4 × t PCLK – 3.0
4 × t PCLK – 3.0
4 × t PCLK – 2
4 × t PCLK – 1
3.0
9.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DPI
(OUTPUT)
t SDSCIM
t SPICHM
t SPICLM
t SPICLKM
t HDSM
t SPITDM
SPICLK
(CP = 0,
CP = 1)
(OUTPUT)
MOSI
(OUTPUT)
t DDSPIDM
t HDSPIDM
CPHASE = 1
t SSPIDM
t HSPIDM
t SSPIDM
t HSPIDM
MISO
(INPUT)
MOSI
(OUTPUT)
t DDSPIDM
t HDSPIDM
CPHASE = 0
t SSPIDM
t HSPIDM
MISO
(INPUT)
Figure 34. SPI Master Timing
Rev. J |
Page 42 of 60 |
July 2013
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