参数资料
型号: ADSP-21363KSWZ-1AA
厂商: Analog Devices Inc
文件页数: 31/60页
文件大小: 0K
描述: IC DSP 32BIT 333MHZ EPAD 144LQFP
产品培训模块: SHARC Processor Overview
标准包装: 1
系列: SHARC®
类型: 浮点
接口: DAI,SPI
时钟速率: 333MHz
非易失内存: ROM(512 kB)
芯片上RAM: 384kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 144-LQFP 裸露焊盘
供应商设备封装: 144-LQFP(20x20)
包装: 托盘
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 26. Serial Ports—External Late Frame Sync
K and B Grade
Y Grade
Parameter Min
Max
Max
Unit
Switching Characteristics
t DDTLFSE 1
Data Delay from Late External Transmit Frame Sync
t DDTENFS 1
or External Receive FS with MCE = 1, MFD = 0
Data Enable for MCE = 1, MFD = 0 0.5
9
10.5
ns
ns
1
The t DDTLFSE and t DDTENFS parameters apply to left-justified sample pair as well as serial mode, and MCE = 1, MFD = 0.
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
DAI_P20–1
(SCLK)
t HFSE/I
t SFSE/I
DAI_P20–1
(FS)
t DDTE/I
DAI_P20–1
t DDTENFS
t HDTE/I
(DATA CHANNEL
1ST BIT
2ND BIT
A/B)
t DDTLFSE
LATE EXTERNAL TRANSMIT FS
DRIVE
SAMPLE
DRIVE
DAI_P20–1
(SCLK)
t HFSE/I
t SFSE/I
DAI_P20–1
(FS)
t DDTE/I
DAI_P20–1
t DDTENFS
t HDTE/I
(DATA CHANNEL
1ST BIT
2ND BIT
A/B)
t DDTLFSE
Figure 22. External Late Frame Sync
Rev. J |
Page 31 of 60 |
July 2013
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