参数资料
型号: ADSP-BF561SKBCZ-6V
厂商: Analog Devices Inc
文件页数: 56/64页
文件大小: 0K
描述: IC DSP 32BIT 600MHZ 256CSPBGA
产品培训模块: Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
标准包装: 1
系列: Blackfin®
类型: 定点
接口: SPI,SSP,UART
时钟速率: 600MHz
非易失内存: 外部
芯片上RAM: 328kB
电压 - 输入/输出: 2.50V,3.30V
电压 - 核心: 1.35V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 256-LFBGA,CSPBGA
供应商设备封装: 256-CSPBGA(12x12)
包装: 托盘
配用: ADZS-BFAUDIO-EZEXT-ND - BOARD EVAL AUDIO BLACKFIN
ADZS-BF561-EZLITE-ND - BOARD EVAL ADSP-BF561
ADZS-BF561-MMSKIT-ND - KIT STARTER MULTIMEDIA BF561
ADZS-BFAV-EZEXT-ND - BOARD DAUGHT ADSP-BF533,37,61KIT
ADSP-BF561 
297-BALL PBGA BALL ASSIGNMENT
Table 39 lists the 297-Ball PBGA ball assignment numerically by
ball number. Table 40 on Page 58 lists the ball assignment
alphabetically by signal.
Table 39. 297-Ball PBGA Ball Assignment (Numerically by Ball Number)
Ball No.
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
Signal
GND
ADDR25
ADDR23
ADDR21
ADDR19
ADDR17
ADDR15
ADDR13
ADDR11
ADDR09
AMS3
AMS1
AWE
ARE
SMS0
SMS2
SRAS
SCAS
SCLK0
SCLK1
BGH
ABE0
ABE2
ADDR08
ADDR06
GND
PPI1CLK
GND
ADDR24
ADDR22
ADDR20
ADDR18
ADDR16
ADDR14
ADDR12
ADDR10
AMS2
AMS0
AOE
ARDY
Ball No.
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C01
C02
C03
C04
C05
C22
C23
C24
C25
C26
D01
D02
D03
D04
D23
D24
D25
D26
E01
E02
E03
E24
E25
E26
F01
F02
F25
F26
Signal
SMS1
SMS3
SCKE
SWE
SA10
BR
BG
ABE1
ABE3
ADDR07
GND
ADDR05
PPI0SYNC3
PPI0CLK
GND
GND
GND
GND
GND
GND
ADDR04
ADDR03
PPI0SYNC1
PPI0SYNC2
GND
GND
GND
GND
ADDR02
DATA1
PPI0D15
PPI0D14
GND
GND
DATA0
DATA3
PPI0D13
PPI0D12
DATA2
DATA5
Ball No.
G01
G02
G25
G26
H01
H02
H25
H26
J01
J02
J10
J11
J12
J13
J14
J15
J16
J17
J18
J25
J26
K01
K02
K10
K11
K12
K13
K14
K15
K16
K17
K18
K25
K26
L01
L02
L10
L11
L12
L13
Signal
PPI0D11
PPI0D10
DATA4
DATA7
BYPASS
RESET
DATA6
DATA9
CLKIN
GND
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
DATA8
DATA11
XTAL
NC
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
DATA10
DATA13
NC
NC
VDDEXT
GND
GND
GND
Ball No.
L14
L15
L16
L17
L18
L25
L26
M01
M02
M10
M11
M12
M13
M14
M15
M16
M17
M18
M25
M26
N01
N02
N10
N11
N12
N13
N14
N15
N16
N17
N18
N25
N26
P01
P02
P10
P11
P12
P13
P14
Signal
GND
GND
GND
GND
VDDINT
DATA12
DATA15
VROUT0
GND
VDDEXT
GND
GND
GND
GND
GND
GND
GND
VDDINT
DATA14
DATA17
VROUT1
PPI0D9
VDDEXT
GND
GND
GND
GND
GND
GND
GND
VDDINT
DATA16
DATA19
PPI0D7
PPI0D8
VDDEXT
GND
GND
GND
GND
Rev. E |
Page 56 of 64 |
September 2009
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