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参数资料
| 型号： | ADSP-BF561SKBCZ-6V |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/64页 |
| 文件大小： | 0K |
| 描述： | IC DSP 32BIT 600MHZ 256CSPBGA |
| 产品培训模块： | Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services |
| 标准包装： | 1 |
| 系列： | Blackfin® |
| 类型： | 定点 |
| 接口： | SPI，SSP，UART |
| 时钟速率： | 600MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 328kB |
| 电压 - 输入/输出： | 2.50V，3.30V |
| 电压 - 核心： | 1.35V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-LFBGA，CSPBGA |
| 供应商设备封装： | 256-CSPBGA（12x12） |
| 包装： | 托盘 |
| 配用： | ADZS-BFAUDIO-EZEXT-ND - BOARD EVAL AUDIO BLACKFIN ADZS-BF561-EZLITE-ND - BOARD EVAL ADSP-BF561 ADZS-BF561-MMSKIT-ND - KIT STARTER MULTIMEDIA BF561 ADZS-BFAV-EZEXT-ND - BOARD DAUGHT ADSP-BF533,37,61KIT |
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ADSP-BF561
flexible configuration and upgradability of system memory
while allowing the core to view all SDRAM as a single, contigu-
ous, physical address space.
The asynchronous memory controller can also be programmed
to control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
64M byte segment regardless of the size of the devices used so
that these banks will only be contiguous if fully populated with
64M bytes of memory.
I/O Memory Space
Blackfin processors do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space. On-
chip I/O devices have their control registers mapped into mem-
ory mapped registers (MMRs) at addresses near the top of the
4G byte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core func-
tions, and the other which contains the registers needed for
setup and control of the on-chip peripherals outside of the core.
The core MMRs are accessible only by the core and only in
supervisor mode and appear as reserved space by on-chip
peripherals. The system MMRs are accessible by the core in
supervisor mode and can be mapped as either visible or reserved
to other devices, depending on the system protection
model desired.
Booting
? Interrupts – Events that occur asynchronously to program
flow. They are caused by timers, peripherals, input pins,
and an explicit software instruction.
Each event has an associated register to hold the return address
and an associated “return from event” instruction. When an
event is triggered, the state of the processor is saved on the
supervisor stack.
The ADSP-BF561 event controller consists of two stages: the
Core Event Controller (CEC) and the System Interrupt Control-
ler (SIC). The Core Event Controller works with the System
Interrupt Controller to prioritize and control all system events.
Conceptually, interrupts from the peripherals enter into the
SIC, and are then routed directly into the general-purpose
interrupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority inter-
rupts (IVG15 –14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the ADSP-BF561. Table 1 describes
the inputs to the CEC, identifies their names in the Event Vector
Table (EVT), and lists their priorities.
Table 1. Core Event Controller (CEC)
The ADSP-BF561 contains a small boot kernel, which config-
ures the appropriate peripheral for booting. If the ADSP-BF561
is configured to boot from boot ROM memory space, the pro-
cessor starts executing from the on-chip boot ROM.
Event Handling
The event controller on the ADSP-BF561 handles all asynchro-
nous and synchronous events to the processor. The
ADSP-BF561 provides event handling that supports both nest-
ing and prioritization. Nesting allows multiple event service
routines to be active simultaneously. Prioritization ensures that
servicing of a higher priority event takes precedence over servic-
ing of a lower priority event. The controller provides support for
five different types of events:
? Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
? Reset – This event resets the processor.
? Nonmaskable Interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
Priority
(0 is Highest)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Event Class
Emulation/Test Control
Reset
Nonmaskable Interrupt
Exceptions
Global Enable
Hardware Error
Core Timer
General Interrupt 7
General Interrupt 8
General Interrupt 9
General Interrupt 10
General Interrupt 11
General Interrupt 12
General Interrupt 13
General Interrupt 14
General Interrupt 15
EVT Entry
EMU
RST
NMI
EVX
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut-
down of the system.
? Exceptions – Events that occur synchronously to program
flow, i.e., the exception will be taken before the instruction
is allowed to complete. Conditions such as data alignment
violations or undefined instructions cause exceptions.
System Interrupt Controller (SIC)
The System Interrupt Controller provides the mapping and
routing of events from the many peripheral interrupt sources to
the prioritized general-purpose interrupt inputs of the CEC.
Although the ADSP-BF561 provides a default mapping, the user
can alter the mappings and priorities of interrupt events by
Rev. E |
Page 6 of 64 |
September 2009
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-BF561SKBCZC70 | 制造商:Analog Devices 功能描述: |
| ADSPBF561SKBCZ-C70 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADSP-BF561SKBCZENG | 制造商:Analog Devices 功能描述:- Trays |
| ADSP-BF561SKBZ500 | 功能描述:IC DSP 32BIT 500MHZ 297PBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:Blackfin® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-BF561SKBZ500 | 制造商:Analog Devices 功能描述:Digital Signal Processor IC |
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