
ADuC845/ADuC847/ADuC848
Rev. B | Page 12 of 108
Pin No:
52-MQFP
Pin No: 56-
LFCSP
Mnemonic
Type1
Description
9
P1.4/AIN5
analog input.
ed with AINCOM or as
the positive input of a fully differential pair when used with AIN6.
h 0
I
On power-on default, P1.4/AIN5 is configured as the AIN5
AIN5 can be used as a pseudo differential input when us
P1.0 has no digital output driver. It can function as a digital input for whic
must be written to the port bit. As a digital input, this pin must be driven high
or low externally.
10
P1.5/AIN6
I
of a fully differential pair when used with AIN5.
h 0
On power-on default, P1.5/AIN6 is configured as the AIN6 analog input.
AIN6 can be used as a pseudo differential input when used with AINCOM or as
the negative input
P1.1 has no digital output driver. It can function as a digital input for whic
must be written to the port bit. As a digital input, this pin must be driven high
or low externally.
11
P1.6/AIN7/IEXC1
I/O
of a fully differential pair when used with AIN8. One or both
On power-on default, P1.6/AIN7 is configured as the AIN7 analog input.
AIN7 can be used as a pseudo differential input when used with AINCOM or as
the positive input
current sources can also be configured at this pin.
P1.6 has no digital output driver. It can, however, function as a digital input for
which 0 must be written to the port bit. As a digital input, this pin must be
driven high or low externally.
12
P1.7/AIN8/IEXC2
I/O
as
ferential pair when used with AIN7. One or
On power-on default, P1.7/AIN8 is configured as the AIN8 analog input.
AIN8 can be used as a pseudo differential input when used with AINCOM or
the negative input of a fully dif
both current sources can also be configured at this pin.
P1.7 has no digital output driver. It can, however, function as a digital input for
which 0 must be written to the port bit. As a digital input, this pin must be
driven high or low externally.
13
AINCOM/DAC
I/O
All analog inputs can be referred to this pin, provided that a relevant pseudo
differential input mode is selected. This pin also functions as an alternative pin
out for the DAC.
14
DAC
O
The voltage output from the DAC, if enabled, appears at this pin.
----
15
AIN9
I
positive input of a fully differential pair when used with
AIN9 can be used as a pseudo differential analog input when used with
AINCOM or as the
AIN10 (LFCSP version only).
----
16
AIN10
I
AIN10 can be used as a pseudo differential analog input when used with
AINCOM or as the negative input of a fully differential pair when used with
AIN9 (LFCSP version only).
15
17
RESET
I
Reset Input. A high level on this pin for 16 core clock cycles while the
oscillator is running resets the device. This pin has an internal weak pull-dow
and a Schmitt trigger input stage.
n
16–
22–25
19
21
.7
ort 3
.
e
18–
24–27
P3.0–P3
I/O
P3.0 to P3.7 are bidirectional port pins with internal pull-up resistors. P
pins that have 1s written to them are pulled high by the internal pull-up
resistors, and in that state can be used as inputs. As inputs, Port 3 pins being
pulled externally low source current because of the internal pull-up resistors
When driving a 0-to-1 output transition, a strong pull-up is active for one cor
clock period of the instruction cycle.
Port 3 pins also have the various secondary functions described below.
16
18
P3.0/RxD
Receiver Data for UART Serial Port.
17
19
P3.1/TxD
Transmitter Data for UART Serial Port.
18
20
P3.2/INT0
r 0.
External Interrupt 0. This pin can also be used as a gate control input to Time
19
21
P3.3/INT1
External Interrupt 1. This pin can also be used as a gate control input to Timer 1.
22
24
P3.4/T0
Timer/Counter 0 External Input.
23
25
P3.5/T1
Timer/Counter 1 External Input.
24
26
P3.6/WR
External Data Memory Write Strobe. This pin latches the data byte from Port 0
into an external data memory.
25
27
P3.7/RD
External Data Memory Read Strobe. This pin enables the data from an external
data memory to Port 0.