参数资料
型号: ADUC845BCPZ8-3
厂商: ANALOG DEVICES INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, QCC56
封装: 8 X 8 MM, LEAD FREE, MO-220-VLLD-2, LFCSP-56
文件页数: 59/108页
文件大小: 1940K
代理商: ADUC845BCPZ8-3
ADuC845/ADuC847/ADuC848
Rev. B | Page 54 of 108
Using the DAC
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier, the functional equivalent
of which is shown in Figure 33.
OUTPUT
BUFFER
HIGH-Z
DISABLE
(FROM MCU)
R
AVDD
VREF
04741-033
14
Figure 33. Resistor String DAC Functional Equivalent
Features of this architecture include inherent guaranteed
monotonicity and excellent differential linearity. As shown in
Figure 33, the reference source for the DAC is user-selectable in
software. It can be either AVDD or VREF. In 0 V-to-AVDD mode,
the DAC output transfer function spans from 0 V to the voltage
at the AVDD pin. In 0 V-to-VREF mode, the DAC output transfer
function spans from 0 V to the internal VREF (2.5 V). The DAC
output buffer amplifier features a true rail-to-rail output stage
implementation. This means that, unloaded, each output is
capable of swinging to within less than 100 mV of both AVDD
and ground. Moreover, the DAC’s linearity specification (when
driving a 10 k resistive load to ground) is guaranteed through
the full transfer function except Codes 0 to 48 in 0 V-to-VREF
mode; Codes 0 to 100; and Codes 3950 to 4095 in 0 V-to-VDD
mode.
Linearity degradation near ground and VDD is caused by satura-
tion of the output amplifier; a general representation of its effects
(neglecting offset and gain error) is shown in Figure 34. The
dotted line indicates the ideal transfer function, and the solid
line represents what the transfer function might look like with
endpoint nonlinearities due to saturation of the output amplifier.
ote that Figure 34 represents a transfer function in 0-to-VDD
REF
< VDD), the lower
ou
e
r, but the upper portion of the
ul
w the ideal line to the end,
th
h-end endpoint linearity error.
N
mode only. In 0 V-to-VREF mode (with V
nonlinearity w
ld b simila
transfer function wo d follo
showing no signs of
e hig
VDD–50mV
VDD
VDD–100mV
100mV
50mV
0mV
000H
FFFH
04741-
034
Figure 34. Endpoint Nonlinearities Due to Amplifier Saturation
The endpoint nonlinearities shown in Figure 34 become worse
as a function of output loading. Most data sheet specifications
assume a 10 k resistive load to ground at the DAC output. As
the output is forced to source or sink more current, the nonlinear
regions at the top or bottom, respectively, of Figure 34 become
larger. With larger current demands, this can significantly limit
output voltage swing. Figure 35 and Figure 36 illustrate this
behavior. Note that the upper trace in each of these figures is
valid only for an output range selection of 0 V to AVDD. In 0 V-
to-VREF mode, DAC loading does not cause high-side voltage
nonlinearities while the reference voltage remains below the
upper trace in the corresponding figure. For example, if AVDD =
3 V and VREF = 2.5 V, the high-side voltage is not affected by
loads of less than 5 mA. But around 7 mA, the upper curve in
Figure 36 drops below 2.5 V (VREF), indicating that at these
higher currents, the output is not capable of reaching VREF.
SOURCE/SINK CURRENT (mA)
5
0
5
10
15
OUTPUT
VOLTAGE
(V)
4
3
2
1
0
DAC LOADED WITH 0000H
DAC LOADED WITH 0FFFH
04741-035
Figure 35. Source and Sink Current Capability with VREF = AVDD = 5 V
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