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| 型号： | ADUC845BCPZ8-3 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, QCC56 |
| 封装： | 8 X 8 MM, LEAD FREE, MO-220-VLLD-2, LFCSP-56 |
| 文件页数： | 25/108页 |
| 文件大小： | 1940K |
| 代理商： | ADUC845BCPZ8-3 |
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ADuC845/ADuC847/ADuC848
Rev. B | Page 23 of 108
11
10
01
00
07H
1FH
00H
08H
0FH
17H
10H
18H
2FH
20H
7FH
30H
FOUR BANKS OF EIGHT
REGISTERS
R0 TO R7
BIT-ADDRESSABLE
(BIT ADDRESSES)
AREA
BANKS
SELECTED
VIA
BITS IN PSW
GENERAL-PURPOSE
RESET VALUE OF
STACK POINTER
04741-008
Figure 8. Lower 128 Bytes of Internal Data Memory
Internal XRAM
The ADuC845, ADuC847, and ADuC848 contain 2 kbytes of
on-chip extended data memory. This memory, although on-
chip, is accessed via the MOVX instruction. The 2 kbytes of
internal XRAM are mapped into the bottom 2 kbytes of the
external address space if the CFG84x.0 (Table 7) bit is set;
otherwise, access to the external data memory occurs just like a
standard 8051.
Even with the CFG84x.0 bit set, access to the external (off chip),
XRAM occurs once the 24-bit DPTR is greater than 0007FFH.
EXTERNAL
DATA
MEMORY
SPACE
(24-BIT
AD
SP
DRESS
ACE)
000000H
FFFFFFH
CFG845/7/8.0 = 0
EXTERNAL
DATA
MEMORY
SPACE
(24-BIT
ADDRESS
SPACE)
000000H
FFFFFFH
CFG845/7/8.0 = 1
0007FFH
000800H
2 kBYTES
ON-CHIP
XRAM
04741-009
Figure 9. Internal and External XRAM
When enabled and when accessing the internal XRAM, the P0
and P2 port pin operations, as well as the RD and WR strobes,
do not operate as a standard 8051 MOVX instruction. This
allows the user to use these port pins as standard I/O. The
internal XRAM can be configured as part of the extended 11-bit
stack pointer. By default, the stack operates exactly like an 8052
in that it rolls over from FFH to 00H in the general-purpose
RAM. On the ADuC845, ADuC847, and ADuC848, however, it
FG845.7/ADuC847.7/ADuC848.7) to
e
R
ssary to extend the 8-bit stack pointer in the SP
SFR into an 11-bit stack pointer.
is possible (by setting C
enable the 11-bit extended stack pointer. In this case, the stack
rolls over from FFH in RAM to 0100H in XRAM.
The 11-bit stack pointer is visible in the SPH and SP SFRs. Th
SP SFR is located at 81H as with a standard 8052. The SPH SF
is located at B7H. The 3 LSBs of the SPH SFR contain the 3
extra bits nece
UPPER 1792
BYTES OF
ON-CHIP XRAM
(DATA + STACK
FOR EXSP = 1,
DATA ONLY
FOR EXSP = 0)
CFG845/7/8.7 = 0
256 BYTES OF
ON-CHIP DATA
RAM
(DATA +
STACK)
LOWER 256
BYTES OF
ON-CHIP XRAM
(DATA ONLY)
00H
FFH
00H
07FFH
100H
04741-010
CFG845/7/8.7 = 1
Figure 10. Extended Stack Pointer Operation
m memory access to the
r,
st like a standard 8051-compatible core, the
848 can access external data
OV
truction. The MOVX instruction
utomatically outputs the various control strobes required to
wever, can access up to
his is an enhancement of
y
ern
y space available on a
ndard 8051-compat
e the Hardware Design
section
acce
rn
ter might need
be prog mmed to g
xt
chin
OVX
peration. This is to account
differi
external RAM access
peeds.
AIT SFR
R Address:
wer-On
ult:
ddres
e:
pecial function register (SFR), when programmed,
dictates the number of wait states for the MOVX instruction.
The value can vary between 0H and 7H. The MOVX instruc-
tion increases by one machine cycle (4 + n, where n = EWAIT
number in decimal) for every increase in the EWAIT value.
External Data Memory (External XRAM)
There is no support for external progra
parts. Howeve ju
ADuC845/ADuC847/ADuC
memory using a M
X ins
a
access the data memory. The parts, ho
16 Mbytes of external data memory. T
the 64 kb tes of ext
al data memor
sta
ible core. Se
for details.
When
ssing exte al RAM, the EWAIT regis
to
ra
ive e ra ma
e cycles to the M
o
for
ng
s
EW
SF
Po
Defa
9FH
00H
Bit A
sabl
No
This s
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