参数资料
型号: ADUC845BCPZ8-3
厂商: ANALOG DEVICES INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, QCC56
封装: 8 X 8 MM, LEAD FREE, MO-220-VLLD-2, LFCSP-56
文件页数: 26/108页
文件大小: 1940K
代理商: ADUC845BCPZ8-3
ADuC845/ADuC847/ADuC848
Rev. B | Page 24 of 108
ERS (SFRs)
ssing only. It
r
n the CPU and all on-chip periph-
m
ing the programming model of the
47/
C848 via the SFR area is shown in
he four
pu
gi
de in the SFR area. The SFR
isters in
nt
a registers that
provide an interface b
erals.
SPECIAL FUNCTION REGIST
The SFR space is mapped into the upper 128 bytes of internal
data memory space and accessed by direct addre
provides an inte face betwee
erals. A block diagra
show
ADuC845/ADuC8
ADu
All registers except the program counter (PC) and t
general-
rpose re ster banks resi
reg
clude co rol, configuration, and dat
etween the CPU and all on-chip periph
128-BYTE
SPECIAL
FUNCTION
REGISTER
AREA
62-kBYTE
ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE PROGRAM
MEMORY
8051-
COMPATIBLE
CORE
OTHER ON-CHIP
RCES
WDT
PSM
TIC
PWM
PERIPHERALS
TEMPERATURE
SENSOR
CURRENT SOU
12-BIT DAC
SERIAL I/O
Σ- ADC
4-kBYTE
ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE DATA
MEMORY
256 BYTES RAM
2kBYTES XRAM
04741-011
Figure 11. Programming Model
Accumulator SFR (ACC)
ACC is the accumulator register, which is used for math opera-
tions including addition, subtraction, integer multiplication and
division, and Boolean bit manipulations. The mnemonics for
accumulator-specific instructions usually refer to the
accumulator as A.
B SFR (B)
The B register is used with the accumulator for multiplication
and division operations. For other instructions, it can be treated
as a general-purpose scratch pad register.
f three 8-bit registers: DPP (page
PP,
C
C848 support dual data
Pointers section.
Stack Pointer (SP and SPH)
RA
ress
of the stack. The SP register
increme
fore
USH and CALL
executions. Although
RAM, the SP register i
his
causes the stack to beg
As mentioned earlier, t
ded 11-bit stack
inter. Th
ree extr
tack
inter are
three L
o
able the
SFR, th
rwise,
SF
om.
ogram Status Word
e PSW S
n
status of the CPU as li
SFR Address:
Power-On Default:
Bit Addressable:
able 5. PSW SFR Bit Designations
Bit No.
Name
Description
Data Pointer (DPTR)
The data pointer is made up o
byte), DPH (high byte), and DPL (low byte). These provide
memory addresses for internal code and data memory access.
The DPTR can be manipulated as a 16-bit register (DPTR =
DPH, DPL), although INC DPTR instructions automatically
carry over to DPP, or as three independent 8-bit registers (D
DPH, DPL).
The ADuC845/ADu 847/ADu
pointers. See the D
The SP SFR is the stack pointer, which is used to hold an
internal
M add
called the top
is
nted be
data is stored during P
the stack can reside anywhere in on-chip
s initialized to 07H after a reset. T
in at location 08H.
he parts offer an exten
po
e th
a bits needed to make up the 11-bit s
po
the
SBs of the SPH byte located at B7H. T
en
SPH
e EXSP (CFG84x.7) bit must be set;
othe
the SPH
R can be neither written to nor read fr
Pr
(PSW)
Th
FR contai s several bits that reflect the current
sted in Table 5.
D0H
00H
Yes
T
7
CY
Carry Flag.
6
AC
Auxiliary Carry Flag.
5
F0
General-Purpose Flag.
4, 3
RS1, RS0
Register Bank Select Bits.
RS1
RS0
Selected Bank
0
1
0
2
1
3
2
OV
Overflow Flag.
1
F1
General-Purpose Flag.
0
P
Parity Bit.
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