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| 型号： | ADUC845BCPZ8-3 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, QCC56 |
| 封装： | 8 X 8 MM, LEAD FREE, MO-220-VLLD-2, LFCSP-56 |
| 文件页数： | 36/108页 |
| 文件大小： | 1940K |
| 代理商： | ADUC845BCPZ8-3 |
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ADuC845/ADuC847/ADuC848
Rev. B | Page 33 of 108
ured is
r has gone open circuit. When the voltage
ndicates that the transducer has gone
tage is below a specified threshold, a
he ADC status register (ADCSTAT),
re clamped, and calibration registers are not
F bit
ord depends on whether
hput
of the Sinc3 filter is a second notch filter
e
E register (ADCMODE.6). The notch is valid only
tch
log
and a measurement of the input voltage on the analog input
channel can be taken. When the resulting voltage meas
full scale, the transduce
measured is 0 V, this i
short circuit. The current sources work over the normal
absolute input voltage range specifications.
REFERENCE DETECT CIRCUIT
The main and auxiliary (ADuC845 only) ADCs can be config-
ured to allow the use of the internal band gap reference or an
external reference that is applied to the REFIN± pins by means
of the XREF0/1 bit in the Control Registers AD0CON2 and
AD1CON (ADuC845 only). A reference detection circuit is
provided to detect whether a valid voltage is applied to the
REFIN± pins. This feature arose in connection with strain-gage
sensors in weigh scales where the reference and signal are
provided via a cable from the remote sensor. It is desirable to
detect whether the cable is disconnected. If either of the pins is
floating or if the applied vol
flag (NOXREF) is set in t
conversion results a
updated if a calibration is in progress.
Note that the reference detect does not look at REFIN2± pins.
If, during either an offset or gain calibration, the NOEXRE
becomes active, indicating an incorrect VREF, updating the
relevant calibration register is inhibited to avoid loading
incorrect data into these registers, and the appropriate bits in
ADCSTAT (ERR0 or ERR1) are set. If the user needs to verify
that a valid reference is in place every time a calibration is
performed, the status of the ERR0 and ERR1 bits should be
checked at the end of every calibration cycle.
SINC FILTER REGISTER (SF)
The number entered into the SF register sets the decimation
The range of operation of the SF w
ADC chop is on or off. With chop disabled, the minimum SF
word is 3 and the maximum is 255. This gives an ADC through-
put rate from 16.06 Hz to 1.365 kHz. With chop enabled, the
minimum SF word is 13 (all values lower than 13 are clamped
to 13) and the maximum is 255. This gives an ADC throug
rate of 5.4 Hz to 105 Hz. See the fADC equation in the ADC
description preceding section.
An additional feature
positioned in the frequency response at 60 Hz. This gives
simultaneous 60 Hz rejection to whatever notch is defined by
the SF filter. This 60 Hz filter is enabled via the REJ60 bit in th
ADCMOD
for SF words ≥ 68; otherwise, ADC errors occur, and, the no
is best used with an SF word of 82d giving simultaneous 50 Hz
and 60 Hz rejection. This function is useful only with an ADC
clock (modulator rate) of 32.768 kHz. During calibration, the
current (user-written) value of the SF register is used.
Σ- MODULATOR
A Σ- ADC usually consists of two main blocks, an ana
modulator, and a digital filter. For the ADuC845/ADuC847/
ADuC848, the analog modulator consists of a difference
amplifier, an integrator block, a comparator, and a feedback
DAC as shown in Figure 16.
INTEGRATOR
AMP
COMPARATOR
DIFFERENCE
ANALOG
INPUT
HIGH
FREQUEN
BIT STREAM
TO DIGITAL
FILTER
DAC
CY
04741-016
Figure 16. Σ- Modulator Simplified Block Diagram
In operation, the analog signal is fed to the difference amplifier
along with the output from the feedback DAC. The difference
between these two signals is integrated and fed to the comparator.
The output from the comparator provides the input to the feed-
back DAC so the system functions as a negative feedback loop
at
r.
d by using a
subsequent digital filter stage. The sampling frequency of the
f the
he
nd-limited, low noise output from the part.
848 filter is a low-pass, Sinc3
z
DE
register (ADCMODE.6). This 60 Hz drop-in notch filter can be
that tries to minimize the difference signal. The digital data th
represents the analog input voltage is contained in the duty
cycle of the pulse train appearing at the output of the comparato
This duty cycle data can be recovered as a data-wor
modulator loop is many times higher than the bandwidth o
input signal. The integrator in the modulator shapes the
quantization noise (that results from the analog-to-digital
conversion) so that the noise is pushed toward one-half of t
modulator frequency.
DIGITAL FILTER
The output of the ∑- modulator feeds directly into the digital
filter. The digital filter then band-limits the response to a
frequency significantly lower than one-half of the modulator
frequency. In this manner, the 1-bit output of the comparator is
translated into a ba
The ADuC845/ADuC847/ADuC
or [(SINx)/x]3 filter whose primary function is to remove the
quantization noise introduced at the modulator. The cutoff
frequency and decimated output data rate of the filter are
programmable via the SF (Sinc filter) SFR as listed in Table 28
and Table 29.
response of the ADC, yielding an overall output rate of 16.6 H
with chop enabled and 50 Hz with chop disabled. Also detailed
in these plots is the effect of the fixed 60 Hz drop-in notch filter
(REJ60 bit, ADCMODE.6). This fixed filter can be enabled or
disabled by setting or clearing the REJ60 bit in the ADCMO
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| ADUC845BS62-3 | 制造商:Analog Devices 功能描述:MCU 8-Bit ADuC8xx 8052 CISC 62KB Flash 3.3V/5V 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:8BIT CISC 62KB FLASH 12.85MHZ 3.3V 52MQFP - Bulk |
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