
ADuC845/ADuC847/ADuC848
Rev. B | Page 13 of 108
Pin No:
52-MQFP
Pin No: 56-
LFCSP
Mnemonic
Type1
Description
20, 34, 48
22, 36, 51
DVDD
S
Digital Supply Voltage.
21, 35, 47
7, 38, 50
23, 3
DGND
S
Digital Ground.
26
28
SCLK (I2C)
I/O
2C Interface. As an input, this pin is a Schmitt-
internal pull-up is present on this pin unless it is
low. This pin can also be controlled in software as a digital
Serial Interface Clock for the I
triggered input. A weak
outputting logic
output pin.
27
29
SDATA
I/O
al
Serial Data Pin for the I2C Interface. As an input, this pin has a weak intern
pull-up present unless it is outputting logic low.
28–31,
39
30–33, 39–
P2.0–P2.7
I/O
irectional port with internal pull-up resistors. Port 2 pins that
2 pins being pulled
36–
42
Port 2 is a bid
have 1s written to them are pulled high by the internal pull-up resistors, and
in that state can be used as inputs. As inputs, Port
externally low source current because of the internal pull-up resistors. Port 2
emits the middle and high-order address bytes during accesses to the 24-bit
external data memory space.
Port 2 pins also have the various secondary functions described below.
28
30
P2.0/SCLOCK (SPI)
l pull-up is present on this pin unless it is
Serial Interface Clock for the SPI Interface. As an input this pin is a Schmitt-
triggered input. A weak interna
outputting logic low.
29
31
P2.1/MOSI
Serial Master Output/Slave Input Data for the SPI Interface. A strong interna
pull-up is present on this pin when the SPI interface outputs a logic high.
strong internal pull-do
l
A
wn is present on this pin when the SPI interface
outputs a logic low.
30
32
P2.2/MISO
Master Input/Slave Output for the SPI Interface. A weak pull-up is present on
this input pin.
31
33
P2.3/SS/T2
Interface. A weak pull-up is present on this pin.
nabled, Counter 2 is incremented in response to a negative
Slave Select Input for the SPI
For both package options, this pin can also be used to provide a clock input to
Timer 2. When e
transition on the T2 input pin.
36
39
P2.4/T2EX
Control Input to Timer 2. When enabled, a negative transition on the T2EX
input pin causes a Timer 2 capture or reload event.
37
40
P2.5/PWM0
0 output appears at this pin.
If the PWM is enabled, the PWM
38
41
P2.6/PWM1
If the PWM is enabled, the PWM1 output appears at this pin.
39
42
P2.7/PWMCLK
provided at this pin.
If the PWM is enabled, an external PWM clock can be
32
34
XTAL1
I
Input to the Crystal Oscillator Inverter.
33
35
XTAL2
O
40
43
EA
External Access Enable, Logic Input. When held high, this input enables the
to
ss is available on the ADuC845,
device to fetch code from internal program memory locations 0000H
F7FFH. No external program memory acce
ADuC847, or ADuC848. To determine the mode of code execution, the EA pin
is sampled at the end of an external RESET assertion or as part of a device
power cycle. EA can also be used as an external emulation I/O pin, and
therefore the voltage level at this pin must not be changed during normal
operation because this might cause an emulation interrupt that halts code
execution.
41
44
PSEN
O
cution.
Program Store Enable, Logic Output. This function is not used on the
ADuC845, ADuC847, or ADuC848. This pin remains high during internal
program exe
PSEN can also be used to enable serial download mode when pulled lo
through a resistor at the end of an external RESET assertion or as part o
device power cycle.
w
f a
42
45
ALE
O
te
ing external data memory access cycles. It can be
Address Latch Enable, Logic Output. This output is used to latch the low by
(and page byte for 24-bit data address space accesses) of the address to
external memory dur
disabled by setting the PCON.4 bit in the PCON SFR.