参数资料
型号: ADUC845BCPZ8-3
厂商: ANALOG DEVICES INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, QCC56
封装: 8 X 8 MM, LEAD FREE, MO-220-VLLD-2, LFCSP-56
文件页数: 58/108页
文件大小: 1940K
代理商: ADUC845BCPZ8-3
ADuC845/ADuC847/ADuC848
Rev. B | Page 53 of 108
DAC CIRCUIT INFORMATION
The ADuC845/ADuC847/ADuC848 incorporate a 12-bit,
voltage output DAC on-chip. It has a rail-to-rail voltage output
buffer capable of driving 10 k/100 pF, and has two selectable
ranges, 0 V to VREF and 0 V to AVDD. It can operate in 12-bit or
8-bit mode. The DAC has a control register, DACCON, and two
data registers, DACH/L. The DAC output can be programmed
to appear at Pin 14 (DAC) or Pin 13 (AINCOM).
In 12-bit mode, the DAC voltage output is updated as soon as
the DACL data SFR is written; therefore, the DAC data registers
should be updated as DACH first, followed by DACL. The 12-
bit DAC data should be written into DACH/L right-justified
such that DACL contains the lower 8 bits, and the lower nibble
of DACH contains the upper 4 bits.
DACCON Control Register
SFR Address:
FDH
Power-On Default:
00H
Bit Addressable:
No
Table 33. DACCON—DAC Configuration Commands
Bit No.
Name
Description
7
–––
Not Implemented. Write Don’t Care.
6
–––
Not Implemented. Write Don’t Care.
5
–––
Not Implemented. Write Don’t Care.
4
DACPIN
DAC Output Pin Select.
Set to 1 by the user to direct the DAC output to Pin 13 (AINCOM).
Cleared to 0 by the user to direct the DAC output to Pin 14 (DAC).
3
DAC8
DAC 8-Bit Mode Bit.
Set to 1 by the user to enable 8-bit DAC operation. In this mode, the 8 bits in DACL SFR are routed to the 8 MSBs
of the DAC, and the 4 LSBs of the DAC are set to 0.
Cleared to 0 by the user to enable 12-bit DAC operation. In this mode, the 8 LSBs of the result are routed to
DACL, and the upper 4 MSB bits are routed to the lower 4 bits of DACH.
2
DACRN
DAC Output Range Bit.
Set to 1 by the user to configure the DAC range of 0 V to AVDD.
Cleared to 0 by the user to configure the DAC range of 0 V to 2.5 V (VREF).
1
DACCLR
DAC Clear Bit.
Set to 1 by the user to enable normal DAC operation.
Cleared to 0 by the user to reset the DAC data registers DACL/H to 0.
0
DACEN
DAC Enable Bit.
Set to 1 by the user to enable normal DAC operation.
Cleared to 0 by the user to power down the DAC.
DACH/DACL Data Registers
These DAC data registers are written to by the user to update
the DAC output.
SFR Address:
DACL (DAC data low byte)—FBH
DACH (DAC data high byte)—FCH
Power-On Default:
00H (both registers)
Bit Addressable:
No (both registers)
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