参数资料
型号: ADUC845BCPZ8-3
厂商: ANALOG DEVICES INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, QCC56
封装: 8 X 8 MM, LEAD FREE, MO-220-VLLD-2, LFCSP-56
文件页数: 45/108页
文件大小: 1940K
代理商: ADUC845BCPZ8-3
ADuC845/ADuC847/ADuC848
Rev. B | Page 41 of 108
N
ADCMODE (ADC MODE REGISTER)
Used to control the operational mode of both ADCs.
SFR Address:
D1H
Power-On Default:
08H
Bit Addressable:
No
Table 24. ADCMODE SFR Bit Designations
Bit No.
ame
Description
7
on’t Care.
––
Not Implemented. Write D
6
REJ60
Hz Notch Select
tting
is bit places a notch
z, allowing simultaneous 50 Hz and 60 Hz
jection at an SF word of 82 d
s 60 Hz notch can be set only if SF ≥68 decimal, that is, the regular
ter n
h must be ≤60 Hz. Th
is placed at 60 Hz only if the device clock is at 32.768 kHz.
Automatic 60
Bit.
Se
th
in the frequency response at 60 H
re
ecimal. Thi
fil
otc
is second notch
5
ADC0EN
imar
DC Enable.
e primary ADC and place it in the mode selected in MD2–MD0 below.
Pr
y A
Set by the user to enable th
Cleared by the user to place the primary ADC into power-down mode.
4
ADC1EN
(A
ry (ADuC845 only) ADC and place it in the mode selected in MD2–MD0
DuC845 only)
Auxiliary (ADuC845 only) ADC Enable.
Set by the user to enable the auxilia
below.
Cleared by the user to place the auxiliary (ADuC845 only) ADC in power-down mode.
3
CHOP
Chop M
t b
ode Disable.
ab
Se
th
y the user to
le cho
llowing a
ree times higher ADC data t
ed with this bit set, giving up to
3 kHz ADC upda
ates.
leared
the use
enable
iary (ADuC845 only) ADC.
dis
p mode on both the primary and auxiliary
hroughput. SF values as low as 3 are allow
(ADuC845 only) ADC a
1.
te r
C
by
r to
chop mode on both the primary and auxil
Primar
d Auxili
ADuC8
ese
select the operation
y an
ary (
45 only) ADC Mode Bits.
Th
bits
al mode of the enabled ADC as follows:
MD2
D1
MD0
M
0
ADC Power-Down Mode (Power-On Default).
0
1
Idle Mo
dulator are held in a reset state
although the modulator clocks are still provided.
de. In idle mode, the ADC filter and mo
0
1
0
Single Conversion Mode. In single conversion mode, a single conversion is performed
on the enabled ADC. Upon completion of a conversion, the ADC data registers
(ADC0H/M/L and/or ADC1H/M/L (ADuC845 only)) are updated. The relevant flags in
the ADCSTAT SFR are written, and power-down is re-entered with the MD2MD0
accordingly being written to 000.
Note that ADC0L is not available on the ADuC848.
0
1
Continuous Conversion. In continuous conversion mode, the ADC data registers are
regularly updated at the selected update rate (see the Sinc Filter SFR Bit Designations
1
0
Internal Zero-Scale Calibration. Internal short automatically connected to the
enabled ADC input(s).
1
0
1
Internal Full-Scale Calibration. Internal or external REFIN± or REFIN2± VREF (as
determined by XREF bits in ADC0CON2 and/or AXREF (ADuC845 only) in ADC1CON
(ADuC845 only) is automatically connected to the enabled ADC input(s) for this
calibration.
1
0
System Zero-Scale Calibration. User should connect system zero-scale input to the
enabled ADC input(s) as selected by CH3–CH0 and ACH3–ACH0 bits in the
ADC0CON2 and ADC1CON (ADuC845 only) registers.
2, 1, 0
MD2, MD1, MD0
1
System Full-Scale Calibration. User should connect system full-scale input to the
enabled ADC input(s) as selected by CH3–CH0 and ACH3–ACH0 bits in the
ADC0CON2 and ADC1CON (ADuC845 only) registers.
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