参数资料
型号: ADUC845BCPZ8-3
厂商: ANALOG DEVICES INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, QCC56
封装: 8 X 8 MM, LEAD FREE, MO-220-VLLD-2, LFCSP-56
文件页数: 46/108页
文件大小: 1940K
代理商: ADUC845BCPZ8-3
ADuC845/ADuC847/ADuC848
Rev. B | Page 42 of 108
ADC o
le to the ADuC845). A write
0
ith no change in contents is also
set.
he exception to this in the third
note of this section.)
1, or if
Cs are also
e
other w
given
e auxilia
requested on the primary ADC
to. Only applicable to the AD
On the other hand, if ADC1C
n to or
ADC1EN is changed from 0 t
, only
auxilia
is reset. For example, if the pr
ary AD is cont
converting when the auxiliary ADC cha
e or en
occur
rimary ADC con
than a
the auxiliary ADC
y A
into step with the outputs of t
m
D
e r
is that the first conversion tim or th
uxili
ADC
delayed by up to three output
hile
uxi
y AD
update rate is synchronized to
e pr
ary A
. Onl
applicable to ADuC845. If the DC1CON wr
ccu
after the primary ADC has co
lete
ts ope
ion, t
auxiliary ADC can respond im edia y with
t havi
to
fall into step with the primary ADCs
tput c le.
parts are powered down via the PD bit in the PCON
register, the current ADCMODE bits are preserved, that is,
they are not reset to default state. Upon a subsequent
resumption of normal operating mode, the ADCs restarts
the selected operation defined by the ADCMODE register.
Once ADCMODE has been written with a calibration
mode, the RDY0/1 (ADuC845 only) bits (ADCSTAT) are
reset and the calibration commences. On completion, the
vant
re
wn mode.
Any calibration request of the auxiliary ADC while the
ature sensor is selected fails to complete. Although
the RDY1 bit is set at the end of the calibration cycle, no
update of the calibration SFRs takes place, and the ERR1
bit is set. ADuC845 only.
maximum SF (see Table 28)
ue (slowest ADC throughput rate) help to ensure
imum calibration.
e duration of a calibration cycle is 2/Fadc for chop-on
de and 4/Fadc for chop-off mode.
Notes on the ADCMODE Register
Any change to the MD bits immediately resets both ADCs
If the
(auxiliary
nly applicab
to the MD2–MD bits w
treated as a re
(See t
If ADC0CON is written when ADC0EN =
ADC0EN is changed from 0 to 1, both AD
imm diately reset. In
priority over th
ords, the primary ADC is
ry ADC and any change
is immediately responded
uC845.
bits in ADCSTAT are written, and the MD2 MD0 bits a
reset to 000B to indicate that the ADC is back in power-
ON is writte
if
do
o 1
the
ry ADC
im
C
inuously
temper
ng
able
s, the p
tinues undisturbed. Rather
llow
to operate with a phase
difference from the primar
DC, the auxiliary ADC falls
he pri ary A C. Th
esult
e f
e a
ary
is
s w
the a
liar
C
th
im
DC
y
A
ite o
rs
mp
d i
rat
he
m
tel
ou
ng
ou
yc
appropriate calibration registers are written, the rele
Calibrations performed at
val
opt
Th
mo
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