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| 型号： | ADUC845BCPZ8-3 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, QCC56 |
| 封装： | 8 X 8 MM, LEAD FREE, MO-220-VLLD-2, LFCSP-56 |
| 文件页数： | 66/108页 |
| 文件大小： | 1940K |
| 代理商： | ADUC845BCPZ8-3 |
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ADuC845/ADuC847/ADuC848
Rev. B | Page 60 of 108
ON-CHIP PLL (PLLCON)
The ADuC845/ADuC847/ADuC848 are intended for use with a
32.768 kHz watch crystal. A PLL locks onto a multiple (384) of
this to provide a stable 12.582912 MHz clock for the system.
The core can operate at this frequency or at binary submultiples
of it to allow power saving when maximum core performance is
not required. The default core clock is the PLL clock divided by
8 or 1.572864 MHz. The ADC clocks are also derived from the
PLL clock, with the modulator rate being the same as the crystal
oscillator frequency. The control register for the PLL is called
PLLCON and is described as follows.
The 5 V parts can be set to a maximum core frequency of
12.58 MHz (CD2...0 = 000) while at 3 V, the maximum core
clock rate is 6.29 MHz (CD2...0 = 001). The CD bits should not
be set to 000b on the 3 V parts.
The 3 V parts are limited to a core clock speed of 6.29 MHz
(CD = 1).
PLLCON PLL Control Register
SFR Address:
D7H
Power-On Default:
53H
Bit Addressable:
No
Table 39. PLLCON PLL Control Register
Bit No.
Name
Description
7
OSC_PD
Oscillator Power-Down Bit.
If low, the 32 kHz crystal oscillator continues running in power-down mode.
If high, the 32.768 kHz oscillator is powered down.
When this bit is low, the seconds counter continues to count in power-down mode and can interrupt the CPU
to exit power-down. The oscillator is always enabled in normal mode.
6
LOCK
PLL Lock Bit. This is a read-only bit.
Set automatically at power-on to indicate that the PLL loop is correctly tracking the crystal clock. After power-
down, this bit can be polled to wait for the PLL to lock.
Cleared automatically at power-on to indicate that the PLL is not correctly tracking the crystal clock. This
might be due to the absence of a crystal clock or an external crystal at power-on. In this mode, the PLL output
can be 12.58 MHz ± 20%. After the part wakes up from power-down, user code can poll this bit to wait for the
PLL to lock. If LOCK = 0, the PLL is not locked.
5
–––
Not Implemented. Write Don’t Care.
4
LTEA
EA Status. Read-only bit. Reading this bit returns the state of the external EA pin latched at reset or power-on.
3
FINT
Fast Interrupt Response Bit.
Set by the user to enable the response to any interrupt to be executed at the fastest core clock frequency.
Cleared by the user to disable the fast interrupt response feature.
This function must not be used on 3 V parts.
CPU (Core Clock) Divider Bits. This number determines the frequency at which the core operates.
CD2
CD1
CD0
Core Clock Frequency (MHz)
0
12.582912. Not a valid selection on 3 V parts.
0
1
6.291456 (Maximum core clock rate allowed on the 3 V parts)
0
1
0
3.145728
0
1
1.572864 (Default core frequency)
1
0
0.786432
1
0
1
0.393216
1
0
0.196608
2, 1, 0
CD2, CD1, CD0
1
0.098304
On 3 V parts (ADuC84xBCPxx-3 or ADuC84xBSxx-3), the CD settings can be only CD = 1; CD = 0 is not a valid
selection. If CD = 0 is selected on a 3 V part by writing to PLLCON, the instruction is ignored, and the previous
CD value is retained.
The Fast Interrupt bit (FINT) must not be used on 3 V parts since it automatically sets the CD bits to 0, which is
not a valid setting.
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