参数资料
型号: ADUC845BCPZ8-3
厂商: ANALOG DEVICES INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 12.58 MHz, MICROCONTROLLER, QCC56
封装: 8 X 8 MM, LEAD FREE, MO-220-VLLD-2, LFCSP-56
文件页数: 33/108页
文件大小: 1940K
代理商: ADUC845BCPZ8-3
ADuC845/ADuC847/ADuC848
Rev. B | Page 30 of 108
Signal Chain Overview with Chop Disabled (CHOP = 1)
With CHOP = 1, chop is disabled and the available output rates
vary from 16.06 Hz to 1.365 kHz. The range of applicable SF
words is from 3 to 255. When switching between channels with
chop disabled, the channel throughput rate is higher than wh
chop is enabled. The drawback with chop disabled is that the
drift performance is degraded and offset calibration is require
following a gain range change or significant temperature
change. A block diagram of the ADC input channel with chop
disable
en
d
d is shown in Figure 15.
ctor is restricted to an 8-bit register SF; the actual decimation
from the Sinc filter (and the ADC conversion rate) is therefore
The signal chain includes a multiplex or buffer, PGA, Σ-Δ
modulator, and digital filter. The modulator bit stream is
applied to a Sinc3 filter. Programming the Sinc3 decimation
fa
factor is the register value times 8. The decimated output rate
3
MOD
ADC
f
×
1
SF
×
8
f
=
e:
is the AD
version rate.
the deci
uivalent of th
loade
e filter
ter, valid ran
rom 3 to 255.
D
is the modulator sampling rate of 32.768 kHz.
r.
cause the
as
wher
fADC
C con
SF is
regis
mal eq
ge is f
e word
d to th
fMO
The settling time to a step input is governed by the digital filte
A synchronized step change requires a settling time of three
times the programmed update rate; a channel change can be
treated as a synchronized step change. This is one conversion
longer than the case for chop enabled. However, be
ADC throughput is three times faster with chop disabled than it
is with chop enabled, the actual time to a settled ADC output is
significantly less also. This means that following a synchronized
step change, the ADC requires three conversions (note: data is
not output following a synchronized ADC change until data h
settled) before the result accurately reflects the new input
voltage.
ADC
SETTLE
t
f
t
×
=
3
An unsynchronized step change requires four conversions to
accur
e new analog input at its output. Note that
ns
d c
AD
ues
t
nd so
mus
settle
s int
t.
in, this is one conversion longer tha
chop
d, but
ause the
through
ith chop
bled is f
than
chop e
d, the ac
me take
btain a
led
C outpu
ss.
The allowable range for SF is 3 to 255 with a default of 69 (45H).
noise
th
n ti
ases
ms
incr
SF.
ately reflect th
with an u ynchronize
hange the
C contin
to outpu
data a
the user
t take un
d output
o accoun
Aga
n with
enable
bec
ADC
put w
disa
aster
with
nable
tual ti
n to o
sett
AD
t is le
The corresponding conversion rates, rms, and peak-to-peak
performances
and Tabl
for each
7. Note that
ent in
e conversio
me incre
by 0.244
em
SINC3 FILTER
PGA
8
× SF
Σ-
MOD
FADC
DIGITAL
OUTPUT
ANALOG
INPUT
MUX
BUF
FMOD
FIN
04741-015
Figure 15. Block Diagram of ADC Input Channel with Chop Disabled
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