- 您现在的位置：买卖IC网 > PDF目录294980 > AGL10002-FFGG256 FPGA, 1000000 GATES, 200 MHz, PBGA144 PDF资料下载
参数资料
| 型号： | AGL10002-FFGG256 |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 1000000 GATES, 200 MHz, PBGA144 |
| 封装： | 13 X 13 MM, 1 MM PITCH, ROHS COMPLIANT, FBGA-144 |
| 文件页数： | 141/204页 |
| 文件大小： | 2800K |
| 代理商： | AGL10002-FFGG256 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页当前第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页第193页第194页第195页第196页第197页第198页第199页第200页第201页第202页第203页第204页
IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
A d v an c ed v0 . 1
2-27
Signal Descriptions for RAM512X185
RAM512X18
has
slightly
different
behavior
than
RAM4K9, as it has dedicated read and write ports.
WW and RW
These signals enable the RAM to be configured in one of
the two allowable aspect ratios (Table 2-9).
WD and RD
These are the input and output data signals, and they
are 18 bits wide. When a 512×9 aspect ratio is used for
write, WD[17:9] are unused and must be grounded. If
this aspect ratio is used for read, RD[17:9] are undefined.
WADDR and RADDR
These are read and write addresses, and they are nine
bits wide. When the 256×18 aspect ratio is used for write
or read, WADDR[8] or RADDR[8] are unused and must be
grounded.
WCLK and RCLK
These signals are the write and read clocks, respectively.
They can be clocked on the rising or falling edge of
WCLK and RCLK.
WEN and REN
These
signals
are
the
write
and
read
enables,
respectively. They are both active low by default. These
signals can be configured as active high.
RESET
This active low signal resets the control logic, forces the
output hold state registers to zero, disables reads and
writes from the SRAM block, and clears the data hold
registers when asserted. It does not reset the contents of
the memory array.
While the RESET signal is active, read and write
operations are disabled. As with any asynchronous reset
signal, care must be taken not to assert it too close to the
edges of active read and write clocks. Refer to the tables
beginning with Table 3-148 on page 3-94 for the
specifications.
PIPE
This signal is used to specify pipelined read on the
output. A LOW on PIPE indicates a nonpipelined read,
and the data appears on the output in the same clock
cycle. A HIGH indicates a pipelined read, and data
appears on the output in the next clock cycle.
Clocking
The dual-port SRAM blocks are only clocked on the rising
edge. SmartGen allows falling-edge-triggered clocks by
adding inverters to the netlist, hence achieving dual-port
SRAM blocks that are clocked on either edge (rising or
falling). For dual-port SRAM, each port can be clocked on
either edge and/or by separate clocks by port.
IGLOO devices support inversion (bubble pushing)
throughout the FPGA architecture, including the clock
input to the SRAM modules. Inversions added to the
SRAM clock pin on the design schematic or in the HDL
code will be automatically accounted for during design
compile without incurring additional delay in the clock
path.
The two-port SRAM can be clocked on the rising or
falling edge of WCLK and RCLK.
If negative-edge RAM and FIFO clocking is selected for
memory macros, clock edge inversion management
(bubble pushing) is automatically used within the IGLOO
development tools, without performance penalty.
Modes of Operation
There are two read modes and one write mode:
Read Nonpipelined (synchronous—1 clock edge):
In the standard read mode, new data is driven
onto the RD bus in the same clock cycle following
RA and REN valid. The read address is registered
on the read port clock active edge, and data
appears at RD after the RAM access time. Setting
PIPE to OFF enables this mode.
Read Pipelined (synchronous—2 clock edges): The
pipelined mode incurs an additional clock delay
from address to data but enables operation at a
much higher frequency. The read address is
registered on the read port active clock edge, and
the read data is registered and appears at RD after
the second read clock edge. Setting PIPE to ON
enables this mode.
Write (synchronous—1 clock edge): On the write
clock active edge, the write data is written into
the SRAM at the write address when WEN is HIGH.
The setup times of the write address, write
enables, and write data are minimal with respect
to the write clock. Write and read transfers are
described with timing requirements in the "DDR
5. The AGL030 device does not support SRAM or FIFO.
Table 2-9 Aspect Ratio Settings for WW[1:0]
WW[1:0]
RW[1:0]
D×W
01
512×9
10
256×18
00, 11
Reserved
相关PDF资料 |
PDF描述 |
|---|---|
| AGL10002-FFGG484I | FPGA, 1000000 GATES, 200 MHz, PBGA484 |
| AGL10002-FFGG484 | FPGA, 1000000 GATES, 200 MHz, PBGA484 |
| AGL10002-FG144I | FPGA, 1000000 GATES, 200 MHz, PBGA144 |
| AGL10002-FG144 | FPGA, 1000000 GATES, 200 MHz, PBGA144 |
| AGL10002-FG256I | FPGA, 1000000 GATES, 200 MHz, PBGA144 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AGL1000V2-CS144 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144ES | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144I | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS144PP | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL1000V2-CS281 | 功能描述:IC FPGA 1KB FLASH 1M 281-CSP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:IGLOO 标准包装:40 系列:SX-A LAB/CLB数:6036 逻辑元件/单元数:- RAM 位总计:- 输入/输出数:360 门数:108000 电源电压:2.25 V ~ 5.25 V 安装类型:表面贴装 工作温度:0°C ~ 70°C 封装/外壳:484-BGA 供应商设备封装:484-FPBGA（27X27） |
发布紧急采购，3分钟左右您将得到回复。