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| 型号： | Enhanced Am486 dx2 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能单片32位微处理器) |
| 中文描述： | 高性能设计的片上集成完整的32位架构Micrprocessor（高性能单片32位微处理器） |
| 文件页数： | 16/69页 |
| 文件大小： | 1068K |
| 代理商： | ENHANCED AM486 DX2 |
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Enhanced Am486 Microprocessor
AMD
16
PRELIMINARY
LOCK
Bus Lock (Active Low; Output)
A Low output on this pin indicates that the current bus
cycle is locked. The microprocessor ignores HOLD
when LOCK is asserted (although it does acknowledge
AHOLD and BOFF). LOCK goes active in the first clock
of the first locked bus cycle and goes inactive after the
last clock of the last locked bus cycle. The last locked
cycle ends when RDY is returned. LOCK is active Low
and is not driven during bus hold. Locked read cycles
are not transformed into cache fill cycles if KEN is active.
M/IO
Memory/Input-Output (Active High/Active Low;
Output)
A High output indicates a memory cycle. A Low output
indicates an I/O cycle.
NMI
Non-Maskable Interrupt (Active High; Input)
A High NMI input signal indicates that an external non-
maskable interrupt has occurred. NMI is rising-edge
sensitive. NMI must be held Low for at least four CLK
periods before this rising edge. The NMI input does not
have an internal pull-down resistor. The NMI input is
asynchronous, but must meet setup and hold times t
20
and t
21
for recognition in any specific clock.
PCD
Page Cache Disable (Active High; Output)
This pin reflects the state of the PCD bit in the page
table entry or page directory entry (programmable
through the PCD bit in CR3). If paging is disabled, the
CPU ignores the PCD bit and drives the PCD output
Low. PCD has the same timing as the cycle definition
pins (M/IO, D/C, and W/R). PCD is active High and is not
driven during bus hold. PCD is masked by the Cache Dis-
able Bit (CD) in Control Register 0 (CR0).
PCHK
Parity Status (Active Low; Output)
Parity status is driven on the PCHK pin the clock after
RDY for read operations. The parity status reflects data sam-
pled at the end of the previous clock. A Low PCHK indicates
a parity error. Parity status is checked only for enabled bytes
as is indicated by the byte enable and bus size signals.
PCHK is valid only in the clock immediately after read data
is returned to the microprocessor; at all other times PCHK is
inactive High. PCHK is floated only during three-state test
mode. (See FLUSH.)
PLOCK – Modified
Pseudo-Lock (Active Low; Output)
In write-back mode, the processor forces the output
High and the signal is always read as inactive. In write-
through mode, PLOCK operates normally. When as-
serted, PLOCK indicates that the current bus transac-
tion requires more than one bus cycle. Examples of
such operations are segment table descriptor reads (8
bytes) and cache line fills (16 bytes). The microproces-
sor drives PLOCK active until the addresses for the last
bus cycle of the transaction have been driven, whether
or not RDY or BRDY is returned. PLOCK is a function
of the BS8, BS16, and KEN inputs. PLOCK should be
sampled on the clock when RDY is returned. PLOCK is
active Low and is not driven during bus hold.
PWT
Page Write-Through (Active High; Output)
This pin reflects the state of the PWT bit in the page
table entry or page directory entry (programmable
through the PWT bit in CR3). If paging is disabled, the
CPU ignores the PWT bit and drives the PWT output
Low. PWT has the same timing as the cycle definition
pins (M/IO, D/C, and W/R). PWT is active High and is not
driven during bus hold.
RESET
Reset (Active High; Input)
RESET forces the microprocessor to initialize. The mi-
croprocessor cannot begin instruction execution of in-
structions until at least 1 ms after V
CC
and CLK have
reached their proper DC and AC specifications. To ensure
proper microprocessor operation, the RESET pin should re-
main active during this time. RESET is active High. RESET
is asynchronous but must meet setup and hold times t
20
and
t
21
to ensure recognition on any specific clock.
RDY
Non-Burst Ready (Active Low; Input)
A Low input on this pin indicates that the current bus
cycle is complete, that is, either the external system has
presented valid data on the data pins in response to a read,
or, the external system has accepted data from the micro-
processor in response to a write. RDY is ignored when the
bus is idle and at the end of the bus cycle’s first clock. RDY
is active during address hold. Data can be returned to
the processor while AHOLD is active. RDY is active Low
and does not have an internal pull-up resistor. RDY must
satisfy setup and hold times t
16
and t
17
for proper chip
operation.
SMI
–
New
SMM Interrupt (Active Low; Input)
A Low signal on the SMI pin signals the processor to enter
System Management Mode (SMM). SMI is the highest level
processor interrupt. The SMI signal is recognized on an in-
struction boundary, similar to the NMI and INTR signals.
SMI is sampled on every rising clock edge. SMI is a falling-
edge sensitive input. Recognition of SMI is guaranteed in
a specific clock if it is asserted synchronously and meets
the setup and hold times. If SMI is asserted asynchronous-
ly, it must go High for a minimum of two clocks before going
Low, and it must remain Low for at least two clocks to guar-
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