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| 型号： | Enhanced Am486 dx2 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能单片32位微处理器) |
| 中文描述： | 高性能设计的片上集成完整的32位架构Micrprocessor（高性能单片32位微处理器） |
| 文件页数： | 38/69页 |
| 文件大小： | 1068K |
| 代理商： | ENHANCED AM486 DX2 |
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Enhanced Am486 Microprocessor
AMD
38
PRELIMINARY
Figure 20. Stop Clock State Machine
(valid for write-back mode only)
Figure 21. Recognition of Inputs when Exiting Stop Grant State
t
20
t
21
CLK
STPCLK
NMI
SMI
A
STPCLK
Sampled
Note:
A = Earliest time at which NMI or SMI is recognized.
A RESET or SRESET brings the CPU from the Stop
Grant state to the Normal state. The CPU recognizes
the inputs required for cache invalidations (HOLD,
AHOLD, BOFF, and EADS) as explained later. The CPU
does not recognize any other inputs while in the Stop Grant
state. Input signals to the
CPU are not recognized until 1 clock
after STPCLK is deasserted (see Figure 21).
While in the Stop Grant state, the CPU does not recog-
nize transitions on the interrupt signals (SMI, NMI, and
INTR). Driving an active edge on either SMI or NMI does not
guarantee recognition and service of the interrupt request fol-
lowing exit from the Stop Grant state. However, if one of the
interrupt signals (SMI, NMI, or INTR) is driven active while the
CPU is in the Stop Grant state, and held active for at least one
CLK after STPCLK is deasserted, the corresponding interrupt
相关PDF资料 |
PDF描述 |
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| Enhanced Am486 dx4 | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能设计片上集成完全32位体系微处理器) |
| EO12 | IRDA INFRARED TRANSCEIVER |
| EOL-62L256 | HT62L256 EOL Notification |
| EP05FA20 | FRD |
| EP05Q03L | SBD |
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| ENHSDURR9 | 制造商:MOLEX/WOODHEAD 功能描述:Ethernet Network Switch 制造商:Molex 功能描述:ETHERNET NETWORK SWITCH, No. of Ports:9, Data Rate Max:100Mbps, Switch Mounting: |
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