- 您现在的位置：买卖IC网 > PDF目录362733 > Enhanced Am486 dx2 (Advanced Micro Devices, Inc.) High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能单片32位微处理器) PDF资料下载
参数资料
| 型号： | Enhanced Am486 dx2 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能单片32位微处理器) |
| 中文描述： | 高性能设计的片上集成完整的32位架构Micrprocessor（高性能单片32位微处理器） |
| 文件页数： | 19/69页 |
| 文件大小： | 1068K |
| 代理商： | ENHANCED AM486 DX2 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页当前第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页
Enhanced Am486 Microprocessor
AMD
19
PRELIMINARY
memory coherency. The write-back cache requires en-
hanced system support because the cache may contain
data that is not identical to data in main memory at the
same address location.
4.5
The Enhanced Am486 microprocessor family write-
back cache coherency protocol reduces bus activity
while maintaining data coherency in a multi-master en-
vironment. The cache coherency protocol offers the fol-
lowing advantages:
Write-Back Cache Protocol
n
No unnecessary bus traffic. The protocol dynamical-
ly identifies shared data to the granularity of a cache
line. This dynamic identification ensures that the traf-
fic on the external bus is the minimum necessary to
ensure coherency.
n
Software-transparent. Because the protocol gives
the appearance of a single unified memory, software
does not have to maintain coherency or identify
shared data. Application software developed for a
system without a cache can run without modification.
Software support is required only in the operating
system to identify non-cacheable data regions.
A modified MESI protocol is implemented on the En-
hanced Am486 microprocessor family for systems with
write-back cache support. MESI allows cache line to
exist in four states: modified, exclusive, shared, and in-
valid. The Enhanced Am486 microprocessor family al-
locates memory in the cache due to a read miss. Write
allocation is not implemented. To maintain coherency
between cache and main memory, the MESI protocol
has the following characteristics:
n
The system memory is always updated for the case
during a snoop when a modified line is hit.
n
If a modified line is hit by another master during
snooping, the master is forced off the bus and the
snooped cache writes back the modified line to the
system memory. After the snooped cache completes
the write, the backed-off bus master restarts the ac-
cess and reads the modified data from memory.
4.5.1
Cache Line Overview
To implement the Enhanced Am486 microprocessor cache
coherency protocol, each tag entry is expanded to 2 bits: S1
and S0. Each tag entry is associated with a cache line. Table
3 shows the cache line organization.
Table 3. Cache Line Organization
Data Words (32 Bits)
Address Tag and Status
Address Tag, S1, S0
D0
D1
D2
D3
4.5.2
A cache line can occupy one of four legal states as
indicated by bits S0 and S1. The line states are shown
in Table 4. Each line in the cache is in one of these
states. The state transition is induced either by the pro-
cessor or during snooping from an external bus master.
Line Status and Line State
4.5.2.1
An invalid cache line does not contain valid data for any
external memory location. An invalid line does not par-
ticipate in the cache coherency protocol.
Invalid
4.5.2.2
An exclusive line contains valid data for some external
memory location. The data exactly matches the data in
the external memory location.
Exclusive
4.5.2.3
A shared line contains valid data for an external memory
location and the data is shared by another cache and
exactly matches the data in the external memory, or
indicates that the cache line is in write-through mode.
Shared
4.5.2.4
A modified line contains valid data for an external mem-
ory location. However, the data does not match the data
in the external location because the processor has mod-
ified the data since it was loaded from the external mem-
ory. A cache that contains a modified line is responsible
for ensuring that the data is properly maintained. This
means that in the case of an external access to that line
from another external bus master, the modified line is
first written back to the external memory before the other
external bus master can complete its access. Table 5
shows the MESI cache line states and the correspond-
ing availability of data.
Modified
Table 4. Legal Cache Line States
S1
S0
0
1
0
1
Line State
Invalid
Exclusive
Modified
Shared
0
0
1
1
相关PDF资料 |
PDF描述 |
|---|---|
| Enhanced Am486 dx4 | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能设计片上集成完全32位体系微处理器) |
| EO12 | IRDA INFRARED TRANSCEIVER |
| EOL-62L256 | HT62L256 EOL Notification |
| EP05FA20 | FRD |
| EP05Q03L | SBD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ENHSAURR8 | 制造商:Molex 功能描述:8 PORT MACHINE MOUNT SWITCH 制造商:Molex 功能描述:COMPUTERS, NETWORK SWITCHES CONNECTIVITY, No. of Ports:8, Data Rate Max:100Mbps, |
| ENHSDURR5 | 制造商:Molex 功能描述:COMPUTERS, NETWORK SWITCHES CONNECTIVITY, No. of Ports:5, Switch Mounting:DIN Ra 制造商:Molex 功能描述:ETHERNET DIN RAIL SWITCH 5PORT |
| ENHSDURR9 | 制造商:MOLEX/WOODHEAD 功能描述:Ethernet Network Switch 制造商:Molex 功能描述:ETHERNET NETWORK SWITCH, No. of Ports:9, Data Rate Max:100Mbps, Switch Mounting: |
| ENI-110 | 功能描述:冲压机与冲模 NON-IMPACT PUNCHDOWN TOOL RoHS:否 制造商:Souriau 大小: 产品:Dies 类型:Crimping 描述/功能: |
| ENICSF2811PBKA | 制造商:Texas Instruments 功能描述: |
发布紧急采购，3分钟左右您将得到回复。