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| 型号： | Enhanced Am486 dx2 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能单片32位微处理器) |
| 中文描述： | 高性能设计的片上集成完整的32位架构Micrprocessor（高性能单片32位微处理器） |
| 文件页数： | 39/69页 |
| 文件大小： | 1068K |
| 代理商： | ENHANCED AM486 DX2 |
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Enhanced Am486 Microprocessor
AMD
39
PRELIMINARY
will be serviced. The Enhanced Am486 CPU product family
requires INTR to be held active until the CPU issues an inter-
rupt acknowledge cycle to guarantee recognition. This condi-
tion also applies to the existing Am486 CPUs.
In the Stop Grant State, the system can stop or change
the CLK input. When the clock stops, the CPU enters
the Stop Clock State. The CPU returns to the Stop Grant
State immediately when the CLK input is restarted. You
must hold the STPCLK input Low until a stabilized fre-
quency has been maintained for at least 1 ms to ensure
that the PLL has had sufficient time to stabilize.
The CPU generates a Stop Grant bus cycle when en-
tering the state from the Normal or the Auto HALT Power
Down state. When the CPU enters the Stop Grant State
from the Stop Clock State or the Stop Clock Snoop
State, the CPU does not generate a Stop Grant bus
cycle.
5.5.3
Stop Clock state is entered from the Stop Grant state by
stopping the CLK input (either logic High or logic Low). None
of the CPU input signals should change state while the CLK
input is stopped. Any transition on an input signal (except IN-
TR) before the CPU has returned to the Stop Grant state may
result in unpredictable behavior. If INTR goes active while the
CLK input is stopped, and stays active until the CPU issues
an interrupt acknowledge bus cycle, it is serviced in the normal
manner. System design must ensure the CPU is in the correct
state prior to asserting cache invalidation or interrupt signals
to the CPU.
Stop Clock State
5.5.4
A HALT instruction causes the CPU to enter the Auto
HALT Power Down state. The CPU issues a normal
HALT bus cycle, and only transitions to the Normal state
when INTR, NMI, SMI, RESET, or SRESET occurs.
Auto Halt Power Down State
The system can generate a STPCLK while the CPU is in
the Auto HALT Power Down state. The CPU generates a Stop
Grant bus cycle when it enters the Stop Grant state from the
HALT state. When the system deasserts the STPCLK inter-
rupt, the CPU returns execution to the HALT state. The CPU
generates a new HALT bus cycle when it re-enters the HALT
state from the Stop Grant state.
5.5.5
Stop Clock Snoop State
(Cache Invalidations)
When the CPU is in the Stop Grant state or the Auto
HALT Power Down state, the CPU recognizes HOLD,
AHOLD, BOFF, and EADS for cache invalidation. When the
systems asserts HOLD, AHOLD, or BOFF the CPU floats the
bus accordingly. When the system asserts EADS, the CPU
transparently enters Stop Clock Snoop state and powers up
for one full clock to perform the required cache snoop cycle.
If a modified line is snooped, a cache write-back occurs with
HITM transitioning active until the completion of the write-
back. It then powers down and returns to the previous state.
The CPU does not generate a bus cycle when it returns to the
previous state.
5.5.6
When configured in write-back mode, the processor rec-
ognizes FLUSH for copying back modified cache lines
to memory in the Auto Halt Power Down State or Normal
State. Upon the completion of the cache flush, the pro-
cessor returns to its prior state, and regenerates a spe-
cial bus cycle, if necessary.
Cache Flush State
6
The Enhanced Am486 microprocessor family supports
a soft reset function through the SRESET pin. SRESET
forces the processor to begin execution in a known
state. The processor state after SRESET is the same
as after RESET except that the internal caches, CD and
NW in CR0, write buffers, SMBASE registers, and float-
ing-point registers retain the values they had prior to
SRESET, and cache snooping is allowed. The proces-
sor starts execution at physical address FFFFFFF0h.
SRESET can be used to help performance for DOS
extenders written for the 80286 processor. SRESET
provides a method to switch from Protected to Real
mode while maintaining the internal caches, CR0, and
the FPU state. SRESET may not be used in place of
RESET after power-up.
SRESET FUNCTION
In write-back mode, once SRESET is sampled active,
the SRESET sequence begins on the next instruction
boundary (unless FLUSH or RESET occur before that
boundary). When started, the SRESET sequence con-
tinues to completion and then normal processor execu-
tion resumes, independent of the deassertion of
SRESET. If a snoop hits a modified line during SRESET,
a normal write-back cycle occurs. ADS is asserted to
drive the bus cycles even if SRESET is not deasserted.
7
7.1
The Enhanced Am486 microprocessor supports four
modes: Real, Virtual, Protected, and System Manage-
ment Mode (SMM).
As an operating mode, SMM has a
distinct processor environment, interface, and hard-
ware/software features. SMM lets the system designer
add new software controlled features to the computer
products that always operate transparent to the Oper-
ating System (OS) and software applications. SMM is
intended for use only by system firmware, not by appli-
cations software or general purpose systems software.
SYSTEM MANAGEMENT MODE
Overview
The SMM architectural extension consists of the follow-
ing elements:
1)
2)
System Management Interrupt (SMI) hardware interface
Dedicated and secure memory space (SMRAM) for
SMI handler code and CPU state (context) data with a
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