参数资料
型号: Enhanced Am486 dx2
厂商: Advanced Micro Devices, Inc.
英文描述: High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能单片32位微处理器)
中文描述: 高性能设计的片上集成完整的32位架构Micrprocessor(高性能单片32位微处理器)
文件页数: 34/69页
文件大小: 1068K
代理商: ENHANCED AM486 DX2
Enhanced Am486 Microprocessor
AMD
34
PRELIMINARY
4.9.3
As with snooping during normal operation, snooping is
permitted during a cache flush, whether initiated by the
FLUSH pin or WBINVD instruction. After completion of
the snoop, and write-back, if needed, the microproces-
sor completes the copy-back of modified cache lines.
Snooping During Cache Flushing
4.10 Burst Write
The Enhanced Am486 microprocessor improves sys-
tem performance by implementing a burst write feature
Table 8. FLUSH Special Bus Cycles
A32–A2
M/IO D/C W/R BE3 BE2 BE1 BE0 Bus Cycle
0000 0001h
0
0
1
0
1
1
1
First Flush
Acknowledge
Second
Flush
Acknowledge
0000 0001h
0
0
1
1
1
0
1
for cache line write-backs and copy-backs. Standard
write operations are still supported because they are on
the Am486DX family of microprocessors. Burst writes
are always four 32-bit words and start at the beginning
of a cache line address of 0 for the starting access. The
timing of the BLAST and BRDY signals is identical to the
burst read. Figure 16 shows a burst write access. (See Figure
17 and Figure 18 for burst read and burst write access with
BOFF asserted.) In addition to using BLAST, the CACHE
signal indicates burstable cycles.
CACHE is a cycle definition pin used when in write-back
mode (CACHE floats in write-through mode). For pro-
cessor-initiated cycles, the signal indicates either
n
for a read cycle, the internal cacheability of the cycle
n
for a write cycle, a burst write-back or copy-back, if
KEN is asserted (for linefills).
W/R
BRDY
ADS
BLAST
ADR
M/IO
XX4
Data
XX0
XX0
XX4
XX8
XXC
Figure 16. Burst Write
CLK
CACHE
XXC
XX8
Data
to CPU
BRDY
BOFF
XX0
XX4
don’t care
ADR
XX0
ADS
BLAST
M/IO
W/R
CLK
XX4
XX4
XX8
XXC
XX4
XX8
XXC
Figure 17. Burst Read with BOFF Assertion
CACHE
相关PDF资料
PDF描述
Enhanced Am486 dx4 High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能设计片上集成完全32位体系微处理器)
EO12 IRDA INFRARED TRANSCEIVER
EOL-62L256 HT62L256 EOL Notification
EP05FA20 FRD
EP05Q03L SBD
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