- 您现在的位置：买卖IC网 > PDF目录362733 > Enhanced Am486 dx2 (Advanced Micro Devices, Inc.) High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能单片32位微处理器) PDF资料下载
参数资料
| 型号： | Enhanced Am486 dx2 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能单片32位微处理器) |
| 中文描述： | 高性能设计的片上集成完整的32位架构Micrprocessor（高性能单片32位微处理器） |
| 文件页数： | 22/69页 |
| 文件大小： | 1068K |
| 代理商： | ENHANCED AM486 DX2 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页当前第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页
Enhanced Am486 Microprocessor
AMD
22
PRELIMINARY
4.8.2.2
The HOLD/HLDA bus arbitration scheme is used prima-
rily in systems where all memory transfers are seen by
the microprocessor. The HOLD/HLDA bus arbitration
scheme permits simple write-back cache design while
maintaining a relatively high performing system. Figure
3 shows a typical system block diagram for HOLD/
HLDA bus arbitration.
HOLD Bus Arbitration Implementation
Note:
To maintain proper system timing, the HOLD
signal must remain active for one clock cycle after HITM
transitions active. Deassertion of HOLD in the same
clock cycle as HITM assertion may ead to unpredictable
processor behavior.
4.8.2.2.1 Processor-Induced Bus Cycles
In the following scenarios, read accesses are assumed
to be cache line fills. The cases also assume that the
core system logic does not return BRDY or RDY until
HITM is sampled. The addition of wait states follows the
standard 486 bus protocol. For demonstration purpos-
es, only the zero wait state approach is shown. Table 6
explains the key to switching waveforms.
CPU
L2 Cache
DRAM
Local Bus
Peripheral
I/O Bus
Interface
Slow
Peripheral
Address Bus
Data Bus
Address Bus
Data Bus
Figure 3. Typical System Block Diagram
for HOLD/HLDA Bus Arbitration
4.8.2.2.2 External Read
Scenario:
The data resides in external memory (see
Figure 4).
Step 1 The processor starts the external read access
by asserting ADS = 0 and W/R = 0.
Step 2 WB/WT is sampled in the same cycle as BRDY If
WB/WT = 1, the data resides in a write-back cache-
able memory location.
Step 3 The processor completes its burst read and as-
serts BLAST.
4.8.2.2.3 External Write
Scenario:
The data is written to the external memory
(see Figure 5).
Step 1 The processor starts the external write access
by asserting ADS = 0 and W/R = 1.
Step 2 The processor completes its write to the core
system logic.
4.8.2.2.4 HOLD/HLDA External Access TIming
In systems with two or more bus masters, each bus
master is equipped with individual HOLD and HLDA
control signals. These signals are then centralized to
the core system logic that controls individual bus mas-
ters, depending on bus request signals and the HITM
signal.
Table 6. Key to Switching Waveforms
Waveform
Inputs
Outputs
Must be steady
Will be steady
May change from
H to L
Will change
from H to L
May change from
L to H
Will change
from L to H
Don’t care; any
change permitted
Changing;
state unknown
Does not apply
Center line is
High-impedance
“Off” state
相关PDF资料 |
PDF描述 |
|---|---|
| Enhanced Am486 dx4 | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能设计片上集成完全32位体系微处理器) |
| EO12 | IRDA INFRARED TRANSCEIVER |
| EOL-62L256 | HT62L256 EOL Notification |
| EP05FA20 | FRD |
| EP05Q03L | SBD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ENHSAURR8 | 制造商:Molex 功能描述:8 PORT MACHINE MOUNT SWITCH 制造商:Molex 功能描述:COMPUTERS, NETWORK SWITCHES CONNECTIVITY, No. of Ports:8, Data Rate Max:100Mbps, |
| ENHSDURR5 | 制造商:Molex 功能描述:COMPUTERS, NETWORK SWITCHES CONNECTIVITY, No. of Ports:5, Switch Mounting:DIN Ra 制造商:Molex 功能描述:ETHERNET DIN RAIL SWITCH 5PORT |
| ENHSDURR9 | 制造商:MOLEX/WOODHEAD 功能描述:Ethernet Network Switch 制造商:Molex 功能描述:ETHERNET NETWORK SWITCH, No. of Ports:9, Data Rate Max:100Mbps, Switch Mounting: |
| ENI-110 | 功能描述:冲压机与冲模 NON-IMPACT PUNCHDOWN TOOL RoHS:否 制造商:Souriau 大小: 产品:Dies 类型:Crimping 描述/功能: |
| ENICSF2811PBKA | 制造商:Texas Instruments 功能描述: |
发布紧急采购，3分钟左右您将得到回复。