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参数资料
| 型号： | Enhanced Am486 dx2 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能单片32位微处理器) |
| 中文描述： | 高性能设计的片上集成完整的32位架构Micrprocessor（高性能单片32位微处理器） |
| 文件页数： | 27/69页 |
| 文件大小： | 1068K |
| 代理商： | ENHANCED AM486 DX2 |
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AMD
27
PRELIMINARY
Enhanced Am486 Microprocessor
Step 1 HOLD places the microprocessor in snooping
mode. HLDA must be High for a minimum of one
clock cycle before EADS assertion. In the fastest
case, this means that HOLD asserts one clock cy-
cle before the HLDA response.
Step 2 EADS and INV are asserted. If INV is 0, snooping
is caused by a read access. If INV is 1, snooping is
caused by a write access. EADS is not sampled
again until after the modified line is written back to
memory. It is detected again as early as in Step 11.
Step 3 Two clock cycles after EADS is asserted, HITM
becomes valid, and is 0 because the line is modi-
fied.
Step 4 In the next clock the core system logic deas-
serts the HOLD signal in response to the HITM =
0. The core system logic backs off the current bus
master at the same time so that the microprocessor
can access the bus. HOLD can be reasserted im-
mediately after ADS is asserted for burst cycles.
Step 5 The snooping cache starts its write-back of the
modified line by asserting ADS = 0, CACHE = 0,
and W/R = 1. The write access is a burst write. The
number of clock cycles between deasserting HOLD
to the snooping cache and first asserting ADS for
the write-back cycles can vary. In this example, it is
one clock cycle, which is the shortest possible time.
Regardless of the number of clock cycles, the start
of the write-back is seen by ADS going Low.
Step 6 The write-back access is finished when BLAST
and BRDY both are 0.
Step 7 In the clock cycle after the final write-back ac-
cess, the processor drives HITM back to 1.
Step 8 HOLD is sampled by the microprocessor.
Step 9 A minimum of 1 clock cycle after the completion
of the pending access, HLDA transitions to 1,
acknowledging the HOLD request.
Step 10 The core system logic removes hold-off control
to the external bus master. This allows the ex-
ternal bus master to immediately retry the abort-
ed access. ADS is strobed Low, which generates
EADS Low in the same clock cycle.
Step 11 The bus master restarts the aborted access.
EADS and INV are applied to the microprocessor
as before. This starts another snoop cycle.
The status of the addressed line is now either shared
(INV = 0) or is changed to invalid (INV = 1).
4.8.5.1
HOLD/HLDA Write-Back Design
Considerations
When designing a write-back cache system that uses
HOLD/HLDA as the bus arbitration method, the follow-
ing considerations must be observed to ensure proper
operation (see Figure 10).
HLDA
CLK
ADS
BLAST
BRDY
HOLD
Valid Hold Assertion
Figure 10. Valid HOLD Assertion During Write-Back
HITM
相关PDF资料 |
PDF描述 |
|---|---|
| Enhanced Am486 dx4 | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能设计片上集成完全32位体系微处理器) |
| EO12 | IRDA INFRARED TRANSCEIVER |
| EOL-62L256 | HT62L256 EOL Notification |
| EP05FA20 | FRD |
| EP05Q03L | SBD |
相关代理商/技术参数 |
参数描述 |
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| ENHSAURR8 | 制造商:Molex 功能描述:8 PORT MACHINE MOUNT SWITCH 制造商:Molex 功能描述:COMPUTERS, NETWORK SWITCHES CONNECTIVITY, No. of Ports:8, Data Rate Max:100Mbps, |
| ENHSDURR5 | 制造商:Molex 功能描述:COMPUTERS, NETWORK SWITCHES CONNECTIVITY, No. of Ports:5, Switch Mounting:DIN Ra 制造商:Molex 功能描述:ETHERNET DIN RAIL SWITCH 5PORT |
| ENHSDURR9 | 制造商:MOLEX/WOODHEAD 功能描述:Ethernet Network Switch 制造商:Molex 功能描述:ETHERNET NETWORK SWITCH, No. of Ports:9, Data Rate Max:100Mbps, Switch Mounting: |
| ENI-110 | 功能描述:冲压机与冲模 NON-IMPACT PUNCHDOWN TOOL RoHS:否 制造商:Souriau 大小: 产品:Dies 类型:Crimping 描述/功能: |
| ENICSF2811PBKA | 制造商:Texas Instruments 功能描述: |
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