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| 型号： | Enhanced Am486 dx2 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能单片32位微处理器) |
| 中文描述： | 高性能设计的片上集成完整的32位架构Micrprocessor（高性能单片32位微处理器） |
| 文件页数： | 5/69页 |
| 文件大小： | 1068K |
| 代理商： | ENHANCED AM486 DX2 |
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AMD
PRELIMINARY
Enhanced Am486 Microprocessor
4.8.9 BOFF During Write-Back .....................................................................................................32
4.8.10 Snooping Characteristics During a Cache Line Fill ...........................................................32
4.8.11 Snooping Characteristics During a Copy-Back .................................................................32
4.9 Cache Invalidation and Flushing in Write-Back Mode ..................................................................33
4.9.1 Cache Invalidation through Software ..................................................................................33
4.9.2 Cache Invalidation through Hardware .................................................................................33
4.9.3 Snooping During Cache Flushing ........................................................................................34
4.10 Burst Write ..................................................................................................................................34
4.10.1 Locked Accesses ..............................................................................................................35
4.10.2 Serialization .......................................................................................................................35
4.10.3 PLOCK Operation in Write-Through Mode ........................................................................36
Clock Control ......................................................................................................................................36
5.1 Clock Generation ..........................................................................................................................36
5.2 Stop Clock .....................................................................................................................................36
5.2.1 External Interrupts in Order of Priority .................................................................................36
5.3 Stop Grant Bus Cycle ...................................................................................................................36
5.4 Pin State during Stop Grant ..........................................................................................................37
5.5 Clock Control State Diagram ........................................................................................................37
5.5.1 Normal State ........................................................................................................................37
5.5.2 Stop Grant State ..................................................................................................................37
5.5.3 Stop Clock State ..................................................................................................................39
5.5.4 Auto Halt Power Down State ...............................................................................................39
5.5.5 Stop Clock Snoop State (Cache Invalidations) ....................................................................39
5.5.6 Cache Flush State ...............................................................................................................39
SRESET Function ...............................................................................................................................39
System Management Mode ................................................................................................................39
7.1 Overview .......................................................................................................................................39
7.2 Terminology ..................................................................................................................................40
7.3 System Management Interrupt Processing ...................................................................................40
7.3.1 System Management Interrupt Processing .........................................................................41
7.3.2 SMI Active (SMIACT) ..........................................................................................................41
7.3.3 SMRAM ...............................................................................................................................42
7.3.4 SMRAM State Save Map ....................................................................................................43
7.4 Entering System Management Mode ............................................................................................44
7.5 Exiting System Management Mode ..............................................................................................44
7.6 Processor Environment .................................................................................................................44
7.7 Executing System Management Mode Handler ............................................................................45
7.7.1 Exceptions and Interrupts with System Management Mode ...............................................46
7.7.2 SMM Revisions Identifier .....................................................................................................46
7.7.3 Auto HALT Restart ..............................................................................................................47
7.7.4 I/O Trap Restart ...................................................................................................................47
7.7.5 I/O Trap Word ......................................................................................................................47
7.7.6 SMM Base Relocation .........................................................................................................48
7.8 SMM System Design Considerations ...........................................................................................48
7.8.1 SMRAM Interface ................................................................................................................48
7.8.2 Cache Flushes ....................................................................................................................49
7.8.3 A20M Pin .............................................................................................................................49
7.8.4 CPU Reset during SMM ......................................................................................................52
7.8.5 SMM and Second Level Write Buffers ................................................................................52
7.8.6 Nested SMI and I/O Restart ................................................................................................52
7.9 SMM Software Considerations .....................................................................................................52
7.9.1 SMM Code Considerations .................................................................................................52
7.9.2 Exception Handling .............................................................................................................52
7.9.3 Halt during SMM ..................................................................................................................53
7.9.4 Relocating SMRAM to an Address above 1 Mbyte .............................................................53
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