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| 型号： | Enhanced Am486 dx2 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能单片32位微处理器) |
| 中文描述： | 高性能设计的片上集成完整的32位架构Micrprocessor（高性能单片32位微处理器） |
| 文件页数： | 48/69页 |
| 文件大小： | 1068K |
| 代理商： | ENHANCED AM486 DX2 |
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Enhanced Am486 Microprocessor
AMD
48
PRELIMINARY
7.7.6
The Enhanced Am486 CPU family provides a new con-
trol register, SMBASE. The SMRAM address space can
be modified by changing the SMBASE register before
exiting an SMI handler routine. SMBASE can be
changed to any 32K-aligned value. (Values that are not
32K-aligned cause the CPU to enter the Shutdown state
when executing the RSM instruction.) SMBASE is set
to the default value of 30000h on RESET. If SMBASE
is changed by an SMI handler, all subsequent SMI re-
quests initiate a state save at the new SMBASE.
SMM Base Relocation
The SMBASE slot in the SMM state save area indicates
and changes the SMI jump vector location and SMRAM
save area. When bit 17 of the SMM Revision Identifier
is set, then this feature exists and the SMRAM base and
consequently, the jump vector, are as indicated by the
SMM Base slot (see Table 15). During the execution of
the RSM instruction, the CPU reads this slot and initial-
izes the CPU to use the new SMBASE during the next
SMI. During an SMI, the CPU does its context save to
the new SMRAM area pointed to by the SMBASE,
stores the current SMBASE in the SMM Base slot (offset
7EF8h), and then starts execution of the new jump vec-
tor based on the current SMBASE (see Figure 30).
The SMBASE must be a 32-Kbyte aligned, 32-bit inte-
ger that indicates a base address for the SMRAM con-
text save area and the SMI jump vector. For example
when the processor first powers up, the minimum SM-
RAM area is from 38000h–3FFFFh. The default SM-
BASE is 30000h.
As illustrated in Figure 31, the starting address of the
jump vector is calculated by:
SMBASE + 8000h
The starting address for the SMRAM state save area is
calculated by:
SMBASE + [8000h + 7FFFh]
When this feature is enabled, the SMRAM register map
is addressed according to the above formula.
Figure 30. SMM Base Slot Offset
31
0
SMM Base
Register Offset 7EF8h
To change the SMRAM base address and SMI jump
vector location, SMI handler modifies the SMBASE slot.
Upon executing an RSM instruction, the processor
reads the SMBASE slot and stores it internally. Upon
recognition of the next SMI request, the processor uses
the new SMBASE slot for the SMRAM dump and SMI
jump vector. If the modified SMBASE slot does not con-
tain a 32-Kbyte aligned value, the RSM microcode caus-
es the CPU to enter the shutdown state.
7.8
7.8.1
The hardware designed to control the SMRAM space
must follow these guidelines:
SMM System Design Considerations
SMRAM Interface
1)
Initialize SMRAM space during system boot up. Initial-
ization must occur before the first SMI occurs. Initializa-
tion of SMRAM space must include installation of an SMI
handler and may include installation of related data struc-
tures necessary for particular SMM applications. The
memory controller interfacing SMRAM should provide a
means for the initialization code to open the SMRAM
space manually.
The memory controller must decode a minimum initial
SMRAM address space of 38000h–3FFFFh.
Alternate bus masters (such as DMA controllers) must
not be able to access SMRAM space. The system
should allow only the CPU, either through SMI or dur-
ing initialization, to access SMRAM.
To implement a 0-V suspend function, the system must
have access to all normal system memory from within
an SMI handler routine. If the SMRAM overlays normal
system memory (see Figure 32), there must be a meth-
od to access overlaid system memory independently.
2)
3)
4)
SMI Handler Entry Point
SMBASE + 8000h
+ 7FFFh
SMRAM
SMBASE + 8000h
SMBASE
Start of State Save
Figure 31. SRAM Usage
相关PDF资料 |
PDF描述 |
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| Enhanced Am486 dx4 | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能设计片上集成完全32位体系微处理器) |
| EO12 | IRDA INFRARED TRANSCEIVER |
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| ENHSDURR9 | 制造商:MOLEX/WOODHEAD 功能描述:Ethernet Network Switch 制造商:Molex 功能描述:ETHERNET NETWORK SWITCH, No. of Ports:9, Data Rate Max:100Mbps, Switch Mounting: |
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