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| 型号： | Enhanced Am486 dx2 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能单片32位微处理器) |
| 中文描述： | 高性能设计的片上集成完整的32位架构Micrprocessor（高性能单片32位微处理器） |
| 文件页数： | 60/69页 |
| 文件大小： | 1068K |
| 代理商： | ENHANCED AM486 DX2 |
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Enhanced Am486 Microprocessor
AMD
60
PRELIMINARY
SWITCHING CHARACTERISTICS for 40 MHz bus (80 MHz or 120 MHz operating frequency)
V
CC
= 3.3 V ± 0.3 V; T
CASE
= 0°C to + 85°C; C
L
= see Note 1
Symbol
Parameter
Min
Max
Unit
Figure
Notes
Frequency
8
40
MHz
Note 2
t
1
CLK Period
25
125
ns
39
t
1a
CLK Period Stability
0.1%
Adjacent Clocks
Notes 3 and 4
t
2
CLK High Time at 2 V
9
ns
39
Note 3
t
3
CLK Low Time at 0.8 V
9
ns
39
Note 3
t
4
CLK Fall Time (2 V–0.8 V)
3
ns
39
Note 3
t
5
CLK Rise Time (0.8 V–2 V)
3
ns
39
Note 3
t
6
A31–A2, PWT, PCD, BE3–BE0, M/IO, D/C, CACHE,
W/R, ADS, LOCK, FERR, BREQ, HLDA,
SMIACT, HITM Valid Delay
3
14
ns
40
Note 5
t
7
A31–A2, PWT, PCD, BE3–BE0, M/IO, D/C, CACHE,
W/R, ADS, LOCK Float Delay
3
18
ns
41
Note 3
t
8
PCHK Valid Delay
3
16
ns
42
t
8a
BLAST, PLOCK, Valid Delay
3
18
ns
40
t
9
BLAST, PLOCK, Float Delay
3
16
ns
41
Note 3
t
10
D31–D0, DP3–DP0 Write Data Valid Delay
3
16
ns
40
t
11
D31–D0, DP3–DP0 Write Data Float Delay
3
18
ns
41
Note 3
t
12
EADS, INV, WB/WT Setup Time
5
ns
43
t
13
EADS, INV, WB/WT Hold Time
3
ns
43
t
14
KEN, BS16, BS8 Setup Time
5
ns
43
t
15
KEN, BS16, BS8 Hold Time
3
ns
43
t
16
RDY, BRDY Setup Time
5
ns
44
t
17
RDY, BRDY Hold Time
3
ns
44
t
18
HOLD, AHOLD Setup Time
6
ns
43
t
18a
BOFF Setup Time
8
ns
43
t
19
HOLD, AHOLD, BOFF Hold Time
3
ns
43
t
20
RESET, FLUSH, A20M, NMI, INTR, IGNNE,
STPCLK, SRESET, SMI Setup Time
5
ns
43
Note 5
t
21
RESET, FLUSH, A20M, NMI, INTR, IGNNE,
STPCLK, SRESET, SMI Hold Time
3
ns
43
Note 5
t
22
D31–D0, DP3–DP0, A31–A4 Read Setup Time
5
ns
43, 44
t
23
D32–D0, DP3–DP0, A31–A4 Read Hold Time
1.
Specifications assume C
L
= 50 pF I/O Buffer model must be used to determine delays due to loading (trace and
component). First Order I/O buffer models for the processor are available.
2.
0 MHz operation guaranteed during stop clock operation.
3.
Not 100% tested. Guaranteed by design characterization.
4.
For faster transitions (>0.1% between adjacent clocks), use the Stop Clock protocol to switch operating frequency.
5.
All timings are referenced at 1.5 V (as illustrated in the listed figures) unless otherwise noted.
3
ns
43, 44
Notes:
相关PDF资料 |
PDF描述 |
|---|---|
| Enhanced Am486 dx4 | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能设计片上集成完全32位体系微处理器) |
| EO12 | IRDA INFRARED TRANSCEIVER |
| EOL-62L256 | HT62L256 EOL Notification |
| EP05FA20 | FRD |
| EP05Q03L | SBD |
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| ENHSDURR9 | 制造商:MOLEX/WOODHEAD 功能描述:Ethernet Network Switch 制造商:Molex 功能描述:ETHERNET NETWORK SWITCH, No. of Ports:9, Data Rate Max:100Mbps, Switch Mounting: |
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