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| 型号： | Enhanced Am486 dx2 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能单片32位微处理器) |
| 中文描述： | 高性能设计的片上集成完整的32位架构Micrprocessor（高性能单片32位微处理器） |
| 文件页数： | 59/69页 |
| 文件大小： | 1068K |
| 代理商： | ENHANCED AM486 DX2 |
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Enhanced Am486 Microprocessor
AMD
59
PRELIMINARY
The AC specifications, provided in the AC characteris-
tics table, consists of output delays, input setup require-
ments, and input hold requirements. All AC
specifications are relative to the rising edge of the CLK
signal. AC specifications measurement is defined by
Figure 36. All timings are referenced to 1.5 V unless
otherwise specified. Enhanced Am486 microprocessor
output delays are specified with minimum and maximum
limits, measured as shown. The minimum microproces-
sor delay times are hold times provided to external cir-
cuitry. Input setup and hold times are specified as
minimums, defining the smallest acceptable sampling
window. Within the sampling window, a synchronous
input signal must be stable for correct microprocessor
operation.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges
Switching Characteristics for 33 MHz bus (66 MHz or 100 MHz operating frequency)
V
CC
= 3.3 V ±0.3 V; T
CASE
= 0°C to + 85°C; C
L
= 50 pF unless otherwise specified
Symbol
Parameter
Min
8
Max
33
Unit
MHz
Figure
Notes
Frequency
Note 2
t
1
CLK Period
30
125
ns
39
t
1a
CLK Period Stability
0.1%
Adjacent Clocks
Notes 3 and 4
t
2
t
3
t
4
t
5
CLK High Time at 2 V
11
ns
39
Note 3
CLK Low Time at 0.8 V
11
ns
39
Note 3
CLK Fall Time (2 V–0.8 V)
3
ns
39
Note 3
CLK Rise Time (0.8 V–2 V)
3
ns
39
Note 3
t
6
A31–A2, PWT, PCD, BE3–BE0, M/IO, D/C, CACHE,
W/R, ADS, LOCK, FERR, BREQ, HLDA,
SMIACT, HITM Valid Delay
3
14
ns
40
Note 5
t
7
A31–A2, PWT, PCD, BE3–BE0, M/IO, D/C, CACHE,
W/R, ADS, LOCK Float Delay
3
20
ns
41
Note 3
t
8
t
8a
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
18a
t
19
PCHK Valid Delay
3
14
ns
42
BLAST, PLOCK, Valid Delay
3
14
ns
40
BLAST, PLOCK, Float Delay
3
20
ns
41
Note 3
D31–D0, DP3–DP0 Write Data Valid Delay
3
14
ns
40
D31–D0, DP3–DP0 Write Data Float Delay
3
20
ns
41
Note 3
EADS, INV, WB/WT Setup Time
5
ns
43
EADS, INV, WB/WT Hold Time
3
ns
43
KEN, BS16, BS8 Setup Time
5
ns
43
KEN, BS16, BS8 Hold Time
3
ns
43
RDY, BRDY Setup Time
5
ns
44
RDY, BRDY Hold Time
3
ns
44
HOLD, AHOLD Setup Time
6
ns
43
BOFF Setup Time
7
ns
43
HOLD, AHOLD, BOFF Hold Time
3
ns
43
t
20
RESET, FLUSH, A20M, NMI, INTR, IGNNE,
STPCLK, SRESET, SMI Setup Time
5
ns
43
Note 5
t
21
RESET, FLUSH, A20M, NMI, INTR, IGNNE,
STPCLK, SRESET, SMI Hold Time
3
ns
43
Note 5
t
22
t
23
D31–D0, DP3–DP0, A31–A4 Read Setup Time
5
ns
43, 44
D32–D0, DP3–DP0, A31–A4 Read Hold Time
1.
Specifications assume C
L
= 50 pF I/O Buffer model must be used to determine delays due to loading (trace and
component). First Order I/O buffer models for the processor are available.
2.
0 MHz operation guaranteed during stop clock operation.
3.
Not 100% tested. Guaranteed by design characterization.
4.
For faster transitions (>0.1% between adjacent clocks), use the Stop Clock protocol to switch operating frequency.
5.
All timings are referenced at 1.5 V (as illustrated in the listed figures) unless otherwise noted.
3
ns
43, 44
Notes:
相关PDF资料 |
PDF描述 |
|---|---|
| Enhanced Am486 dx4 | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能设计片上集成完全32位体系微处理器) |
| EO12 | IRDA INFRARED TRANSCEIVER |
| EOL-62L256 | HT62L256 EOL Notification |
| EP05FA20 | FRD |
| EP05Q03L | SBD |
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