- 您现在的位置：买卖IC网 > PDF目录362733 > Enhanced Am486 dx4 (Advanced Micro Devices, Inc.) High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能设计片上集成完全32位体系微处理器) PDF资料下载
参数资料
| 型号： | Enhanced Am486 dx4 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能设计片上集成完全32位体系微处理器) |
| 中文描述： | 高性能设计的片上集成完整的32位架构Micrprocessor（高性能设计片上集成完全32位体系微处理器） |
| 文件页数： | 13/69页 |
| 文件大小： | 1068K |
| 代理商： | ENHANCED AM486 DX4 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页
Enhanced Am486 Microprocessor
AMD
13
PRELIMINARY
3
The Enhanced Am486 microprocessor family adds ten
signals to those used by the Am486DX processor.
These added signals support the enhanced processor
features and are indicated as “New” in the pin descrip-
tion titles. Some Am486DX CPU signals have new func-
tions to implement the Enhanced Am486 processor
write-back cache protocol. These signals are indicated
as “Modified” in the pin description titles. All other pro-
cessor signals provide the same functionality as the
Am486DX processor.
PIN DESCRIPTION
A20M
Address Bit 20 Mask (Active Low; Input)
A Low signal on the A20M pin causes the microproces-
sor to mask address line A20 before performing a lookup to
the internal cache, or driving a memory cycle on the bus.
Asserting A20M causes the processor to wrap the address
at 1 Mbyte, emulating Real mode operation. The signal is
asynchronous, but must meet setup and hold times t
20
and
t
21
for recognition during a specific clock. During normal op-
eration, A20M should be sampled High at the falling edge of
RESET.
A31–A4/A3–A2
Address Lines (Inputs/Outputs)/(Outputs)
Pins A31–A2 define a physical area in memory or indi-
cate an input/output (I/O) device. Address lines A31–A4
drive addresses into the microprocessor to perform
cache line invalidations. Input signals must meet setup
and hold times t
22
and t
23
. A31–A2 are not driven during
bus or address hold.
ADS
Address Status (Active Low; Output)
A Low output from this pin indicates that a valid bus
cycle definition and address are available on the cycle
definition lines and address bus. ADS is driven active by
the same clock as the addresses. ADS is active Low and is
not driven during bus hold.
AHOLD
–
Modified
Address Hold (Active High; Input)
The external system may assert AHOLD to perform a
cache snoop. In response to the assertion of AHOLD,
the microprocessor stops driving the address bus A31–
A2 in the next clock. The data bus remains active and
data can be transferred for previously issued read or
write bus cycles during address hold. AHOLD is recog-
nized even during RESET and LOCK. The earliest that
AHOLD can be deasserted is two clock cycles after
EADS is asserted to start a cache snoop. If HITM is
activated due to a cache snoop, the microprocessor
completes the current bus activity and then asserts ADS
and drives the address bus while AHOLD is active. This
starts the write-back of the modified line that was the
target of the snoop.
BE3
–
BE0
Byte Enable (Active Low; Outputs)
The byte enable pins indicate which bytes are enabled
and active during read or write cycles. During the first
cache fill cycle, however, an external system should ig-
nore these signals and assume that all bytes are active.
n
BE3 for D31–D24
n
BE2 for D23–D16
n
BE1 for D15–D8
n
BE0 for D7–D0
BE3–BE0 are active Low and are not driven during bus
hold.
BLAST
–
Modified
Burst Last (Active Low; Output)
Burst Last goes Low to tell the CPU that the next BRDY
signal completes the burst bus cycle. BLAST is active for both
burst and non-burst cycles. BLAST is active Low and is not
driven during a bus hold.
BOFF
Back Off (Active Low; Input)
This input signal forces the microprocessor to float all
pins normally floated during hold, but HLDA is not as-
serted in response to BOFF. BOFF has higher priority
than RDY or BRDY; if both are returned in the same
clock, BOFF takes effect. The microprocessor remains
in bus hold until BOFF goes High. If a bus cycle is in
progress when BOFF is asserted, the cycle restarts.
BOFF must meet setup and hold times t
18
and t
19
for
proper operation. BOFF has an internal weak pull-up.
BRDY
Burst Ready Input (Active Low; Input)
The BRDY signal performs the same function during a burst
cycle that RDY performs during a non-burst cycle. BRDY
indicates that the external system has presented valid
data in response to a read, or that the external system
has accepted data in response to write. BRDY is ignored
when the bus is idle and at the end of the first clock in
a bus cycle. BRDY is sampled in the second and sub-
sequent clocks of a burst cycle. The data presented on
the data bus is strobed into the microprocessor when
BRDY is sampled active. If RDY is returned simulta-
neously with BRDY, BRDY is ignored and the cycle is
converted to a non-burst cycle. BRDY is active Low and
has a small pull-up resistor, and must satisfy the setup
and hold times t
16
and t
17
.
BREQ
Internal Cycle Pending (Active High; Output)
BREQ indicates that the microprocessor has generated
a bus request internally, whether or not the microproces-
sor is driving the bus. BREQ is active High and is floated
only during three-state test mode. (See FLUSH.)
相关PDF资料 |
PDF描述 |
|---|---|
| EO12 | IRDA INFRARED TRANSCEIVER |
| EOL-62L256 | HT62L256 EOL Notification |
| EP05FA20 | FRD |
| EP05Q03L | SBD |
| EP05Q06 | SBD Type : EP05Q06 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ENHSAURR8 | 制造商:Molex 功能描述:8 PORT MACHINE MOUNT SWITCH 制造商:Molex 功能描述:COMPUTERS, NETWORK SWITCHES CONNECTIVITY, No. of Ports:8, Data Rate Max:100Mbps, |
| ENHSDURR5 | 制造商:Molex 功能描述:COMPUTERS, NETWORK SWITCHES CONNECTIVITY, No. of Ports:5, Switch Mounting:DIN Ra 制造商:Molex 功能描述:ETHERNET DIN RAIL SWITCH 5PORT |
| ENHSDURR9 | 制造商:MOLEX/WOODHEAD 功能描述:Ethernet Network Switch 制造商:Molex 功能描述:ETHERNET NETWORK SWITCH, No. of Ports:9, Data Rate Max:100Mbps, Switch Mounting: |
| ENI-110 | 功能描述:冲压机与冲模 NON-IMPACT PUNCHDOWN TOOL RoHS:否 制造商:Souriau 大小: 产品:Dies 类型:Crimping 描述/功能: |
| ENICSF2811PBKA | 制造商:Texas Instruments 功能描述: |
发布紧急采购，3分钟左右您将得到回复。