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| 型号： | Enhanced Am486 dx4 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能设计片上集成完全32位体系微处理器) |
| 中文描述： | 高性能设计的片上集成完整的32位架构Micrprocessor（高性能设计片上集成完全32位体系微处理器） |
| 文件页数： | 26/69页 |
| 文件大小： | 1068K |
| 代理商： | ENHANCED AM486 DX4 |
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AMD
26
Enhanced Am486 Microprocessor
Step 3 Two clock cycles after EADS is asserted, HITM
becomes valid, and is 0 because the line is modi-
fied.
Step 4 The core system logic deasserts, in the next
clock, the HOLD signal in response to the HITM =
0 signal. The core system logic backs off the current
bus master at the same time so that the micropro-
cessor can access the bus. HOLD can be reassert-
ed immediately after ADS is asserted for burst
cycles.
Step 5 The snooping cache starts its write-back of the
modified line by asserting ADS = 0, CACHE = 0,
and W/R = 1. The write access is a burst write. The
number of clock cycles between deasserting HOLD
to the snooping cache and first asserting ADS for
the write-back cycles can vary. In this example, it is
one clock cycle, which is the shortest possible time.
Regardless of the number of clock cycles, the start
of the write-back is seen by ADS going Low.
Step 6 The write-back access is finished when BLAST
and BRDY both are 0.
Step 7 In the clock cycle after the final write-back ac-
cess, the processor drives HITM back to 1.
Step 8 HOLD is sampled by the microprocessor.
Step 9 One cycle after sampling HOLD High, the mi-
croprocessor transitions HLDA transitions to 1,
acknowledging the HOLD request.
Step 10 The core system logic removes hold-off control
to the external bus master. This allows the ex-
ternal bus master to immediately retry the abort-
ed access. ADS is strobed Low, which generates
EADS Low in the same clock cycle.
Step 11 The bus master restarts the aborted access.
EADS and INV are applied to the microprocessor
as before. This starts another snoop cycle.
The status of the addressed line is now either shared
(INV = 0) or is changed to invalid (INV = 1).
4.8.5
Scenario
: The following occurs when, in addition to the write-
back operation, other bus accesses initiated by the processor
associated with the snooped cache are pending. The micro-
processor gives the write-back access priority. This implies
that if HOLD is deasserted, the microprocessor first writes
back the modified line (see Figure 9).
Write-Back and Pending Access
Figure 9. Write-Back and Pending Access
Note:
The circled numbers in this figure represent the steps in section 4.8.5.
EADS
External
bus master’s
BOFF signal
HLDA
Data
HOLD
HITM
ADS
INV
BRDY
BLAST
W/R
M/IO
CACHE
ADR
CLK
valid
n
n
n
n+4
n+8
n+12
n+12
valid
n
2
3
1
7
8
9
10
6
5
11
floating/three-stated
4
n+8
n+4
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