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| 型号： | Enhanced Am486 dx4 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能设计片上集成完全32位体系微处理器) |
| 中文描述： | 高性能设计的片上集成完整的32位架构Micrprocessor（高性能设计片上集成完全32位体系微处理器） |
| 文件页数： | 42/69页 |
| 文件大小： | 1068K |
| 代理商： | ENHANCED AM486 DX4 |
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Enhanced Am486 Microprocessor
AMD
42
PRELIMINARY
CLK
CLK2
SMI
SMIACT
ADS
RDY
T1
T2
Normal State
State
Save
SMM
Handler
State
Restore
Normal
State
E
Clock-Doubled CPU
2 CLKs minimum
20 CLKs minimum
139 CLKs
User-determined
236 CLKs
2 CLKs minimum
20 CLKs minimum
Clock-Tripled CPU
2 CLKs minimum
15 CLKs minimum
100 CLKs
User-determined
180 CLKs
2 CLKs minimum
20 CLKs minimum
A: Last RDY from non-SMM transfer to SMIACT assertion
B: SMIACT assertion to first ADS for SMM state save
C: SMM state save (dependent on memory performance)
D: SMI handler
E: SMM state restore (dependent on memory performance)
F: Last RDY from SMM transfer to deassertion of SMIACT
G: SMIACT deassertion of first non-SMM ADS
Figure 25. SMIACT Timing
S S
S S
SS
SS
SS
SS
S S
SS
D
C
A
B
G
F
7.3.3
The CPU uses the SMRAM space for state save and
state restore operations during an SMI. The SMI han-
dler, which also resides in SMRAM, uses the SMRAM
space to store code, data, and stacks. In addition, the
SMI handler can use the SMRAM for system manage-
ment information such as the system configuration, con-
figuration of a powered-down device, and system
designer-specific information.
SMRAM
Note:
Access to SMRAM is through the CPU internal
cache. To ensure cache consistency and correct oper-
ation, always assert the FLUSH pin in the same clock
as SMI for systems using overlaid SMRAM.
The CPU asserts SMIACT to indicate to the memory con-
troller that it is operating in System Management Mode. The
system logic should ensure that only the CPU and SMI han-
dler have access to this area. Alternate bus masters or DMA
devices trying to access the SMRAM space when SMIACT
is active should be directed to system RAM in the respective
area. The system logic is minimally required to decode
the physical memory address range from 38000h–
3FFFFh as SMRAM area. The CPU saves its state to
the state save area from 3FFFFh downward to 3FE00h.
After saving its state, the CPU jumps to the address
location 38000h to begin executing the SMI handler. The
system logic can choose to decode a larger area of SM-
RAM as needed. The size of this SMRAM can be be-
tween 32 Kbytes and 4 Gbytes.The system logic should
provide a manual method for switching the SMRAM into
system memory space when the CPU is not in SMM.
This enables initialization of the SMRAM space (i.e.,
loading SMI handler) before executing the SMI handler
during SMM (see Figure 26).
SMRAM
System memory
accesses redirected
to SMRAM
System memory
accesses not
redirected to SMRAM
CPU
accesses to
system
address
space used
for loading
SMRAM
Normal
Memory
Space
Figure 26. Redirecting System Memory
Address to SMRAM
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