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| 型号： | Enhanced Am486 dx4 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能设计片上集成完全32位体系微处理器) |
| 中文描述： | 高性能设计的片上集成完整的32位架构Micrprocessor（高性能设计片上集成完全32位体系微处理器） |
| 文件页数： | 43/69页 |
| 文件大小： | 1068K |
| 代理商： | ENHANCED AM486 DX4 |
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Enhanced Am486 Microprocessor
AMD
43
PRELIMINARY
7.3.4
When SMI is recognized on an instruction boundary, the
CPU core first sets the SMIACT signal Low, indicating to
the system logic that accesses are now being made to
the system-defined SMRAM areas. The CPU then
writes its state to the state save area in the SMRAM.
The state save area starts at SMBASE + [8000h +
7FFFh]. The default CS Base is 30000h; therefore, the
default state save area is at 3FFFFh. In this case, the
CS Base is also referred to as the SMBASE.
SMRAM State Save Map
Table 10. SMRAM State Save Map
Register
Offset*
7FFCh
CRO
7FF8h
CR3
7FF4h
EFLAGS
7FF0h
EIP
7FECh
EDI
7FE8h
ESI
7FE4h
EBP
7FE0h
ESP
7FDCh
EBX
7FD8h
EDX
7FD4h
ECX
7FD0h
EAX
7FCCh
DR6
7FC8h
DR7
7FC4h
TR*
7FC0h
LDTR*
7FBCh
GS*
7FB8h
FS*
7FB4h
DS*
7FB0h
SS*
7FACh
CS*
7FA8h
ES*
7FA7h–7F98h Reserved
7F94h
IDT Base
7F93h–7F8Ch Reserved
7F88h
GDT Base
7F87h–7F08h
Reserved
7F04h
I/O Trap Word
7F02h
Halt Auto Restart
7F00h
I/O Trap Restart
7EFCh
SMM Revision Identifier
7EF8h
State Dump Base
7EF7h–7E00h Reserved
Note:
*Upper 2 bytes are not modified.
Register
Writable
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
No
If the SMBASE relocation feature is enabled, the SM-
RAM addresses can change. The following formula is
used to determine the relocated addresses where the
context is saved: SMBASE + [8000h + Register Offset],
where the default initial SMBASE is 30000h and the
Register Offset is listed in Table 10. Reserved spaces
are for new registers in future CPUs. Some registers in
the SMRAM state save area may be read and changed
by the SMI handler, with the changed values restored
to the processor register by the RSM instruction. Some
register images are read-only, and must not be modified.
(Modifying these registers results in unpredictable be-
havior.) The values stored in the “reserved” areas may
change in future CPUs. An SMI handler should not rely
on values stored in a reserved area.
The following registers are written out during SMSAVE
mode to the RESERVED memory locations (7FA7h–
7F98h, 7F93h–7F8Ch, and 7F87h–7F08h), but are not
visible to the system software programmer:
n
DR3–DR0
n
CR2
n
CS, DS, ES, FS, GS, and SS hidden descriptor
registers
n
EIP_Previous
n
GDT Attributes and Limits
n
IDT Attributes and Limits
n
LDT Attributes, Base, and Limits
n
TSS Attributes, Base, and Limits
If an SMI request is issued to power down the CPU, the
values of all reserved locations in the SMM state save
must be saved to non-volatile memory.
The following registers are not automatically saved and
restored by SMI and RSM:
n
TR7–TR3
n
FPU registers:
— STn
— FCS
— FSW
— Tag Word
— FP instruction pointer
— FP opcode
— Operand pointer
Note:
You can save the FPU state by using an FSAVE
or FNSAVE instruction.
For all SMI requests except for power down suspend/
resume, these registers do not have to be saved be-
cause their contents will not change. During a power
down suspend/resume, however, a resume reset clears
these registers back to their default values. In this case,
the suspend SMI handler should read these registers
directly to save them and restore them during the power
up resume. Anytime the SMI handler changes these
registers in the CPU, it must also save and restore them.
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