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| 型号： | Enhanced Am486 dx4 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能设计片上集成完全32位体系微处理器) |
| 中文描述： | 高性能设计的片上集成完整的32位架构Micrprocessor（高性能设计片上集成完全32位体系微处理器） |
| 文件页数： | 56/69页 |
| 文件大小： | 1068K |
| 代理商： | ENHANCED AM486 DX4 |
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Enhanced Am486 Microprocessor
AMD
ENHANCED Am486 CPU
IDENTIFICATION
The Enhanced Am486 microprocessor supports two
standard methods for identifying the CPU in a system.
The reported values are dynamically assigned based
on the CPU type (DX2 or DX4) and the status of the
WB/WT pin input (Low = write-through; High = write-
back) at RESET.
56
PRELIMINARY
10
10.1 DX Register at RESET
The DX register always contains a component identifier
at the conclusion of RESET. The upper byte of DX (DH)
contains 04 and the lower byte of DX (DL) contains a
CPU type/stepping identifier (see Table 19).
10.2 CPUID Instruction
The Enhanced Am486 microprocessor family imple-
ments a new instruction that makes information avail-
able to software about the family, model and stepping
of the microprocessor on which it is executing. Support
of this instruction is indicated by the presence of a user-
modifiable bit in position EFLAGS.21, referred to as the
EFLAGS.ID bit. This bit is reset to zero at device reset
(RESET or SRESET) for compatibility with existing pro-
cessor designs.
10.2.1 CPUID Timing
CPUID execution timing depends on the selected EAX
parameter values (see Table 20).
10.2.2 CPUID Operation
The CPUID instruction requires the user to pass an input
parameter to the CPU in the EAX register. The CPU
response is returned to the user in registers EAX, EBX,
ECX, and EDX.
Table 19. CPU ID Codes
CPU Type and Cache Mode
Component
ID (DH)
Revision
ID (DL)
DX2 in write-through mode
04
3x
DX2 in write-back mode
04
7x
DX4 in write-through mode
04
8x
DX4 in write-back mode
04
9x
Table 20. CPUID Instruction Description
OP
Code
Instruction
EAX
Input
Value
0
1
>1
CPU
Core
Clocks
41
14
9
Description
0F A2 CPUID
AMD string
CPU ID Register
null registers
When the parameter passed in EAX is zero, the register
values returned upon instruction execution are:
The values in EBX, ECX, and EDX indicate an AMD
microprocessor. When taken in the proper order:
n
EBX (least significant bit to most significant bit)
n
EDX (least significant bit to most significant bit)
n
ECD (least significant bit to most significant bit)
they decode to:
‘AuthenticAMD’
When the parameter passed in EAX is 1, the register
values returned are:
The value returned in EAX after CPUID instruction ex-
ecution is identical to the value loaded into EDX upon
device reset. Software must avoid any dependency
upon the state of reserved processor bits.
When the parameter passed in EAX s greater than one,
register values returned upon instruction execution are:
EAX[31:0]
EBX[31:0]
ECX[31:0]
EDX[31:0]
00000001h
68747541h
444D4163h
69746E65h
EAX[3:0]
EAX[7:4]
Stepping ID*
Model:
Enhanced Am486 DX2 CPU—
write-through mode = 3h
write-back mode = 7h
Enhanced Am486 DX4 CPU—
write-through mode = 8h
write-back mode = 9h
Family
Am486 CPU = 4h
0000
RESERVED
00000000h
00000000h
00000001h = all versions
The 1 in bit 0 indicates that the
FPU is present
EAX[11:8]
EAX[15:12]
EAX[31:16]
EBX[31:0]
ECX[31:0]
EDX[31:0]
Note:
*Please contact AMD for stepping ID details.
EAX[31:0]
EBX[31:0]
ECX[31:0]
EDX[31:0]
Flags affected
: No flags are affected.
Exceptions
: None
00000000h
00000000h
00000000h
00000000h
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