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| 型号： | Enhanced Am486 dx4 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能设计片上集成完全32位体系微处理器) |
| 中文描述： | 高性能设计的片上集成完整的32位架构Micrprocessor（高性能设计片上集成完全32位体系微处理器） |
| 文件页数： | 36/69页 |
| 文件大小： | 1068K |
| 代理商： | ENHANCED AM486 DX4 |
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Enhanced Am486 Microprocessor
AMD
36
PRELIMINARY
4.10.3 PLOCK Operation in Write-Through Mode
As described in Section 3, PLOCK is only used in write-
through mode; the signal is driven inactive in write-back
mode. In write-through mode, the processor drives
PLOCK Low to indicate that the current bus transaction
requires more than one bus cycle. The CPU continues
to drive the signal Low until the transaction is completed,
whether or not RDY or BRDY is returned. Refer to the
pin description for additional information.
5
5.1
The Enhanced Am486 CPU is driven by a 1X clock that
relies on phased-lock loop (PLL) to generate the two
internal clock phases: phase one and phase two. The
rising edge of CLK corresponds to the start of phase
one (ph1). All external timing parameters are specified
relative to the rising edge of CLK.
CLOCK CONTROL
Clock Generation
5.2
The Enhanced Am486 CPU also provides an interrupt
mechanism, STPCLK, that allows system hardware to con-
trol the power consumption of the CPU by stopping the internal
clock to the CPU core in a sequenced manner. The first low-
power state is called the Stop Grant state. If the CLK input is
completely stopped, the CPU enters into the Stop Clock state
(the lowest power state). When the CPU recognizes a STP-
CLK interrupt, the processor:
Stop Clock
n
stops execution on the next instruction boundary
(unless superseded by a higher priority interrupt).
n
waits for completion of cache flush.
n
stops the pre-fetch unit.
n
empties all internal pipelines and write buffers.
n
generates a Stop Grant bus cycle.
n
stops the internal clock.
At this point the CPU is in the Stop Grant state.
The CPU cannot respond to a STPCLK request from an
HLDA state because it cannot empty the write buffers and,
therefore, cannot generate a Stop Grant cycle. The rising
edge of STPCLK signals the CPU to return to program exe-
cution at the instruction following the interrupted instruction.
Unlike the normal interrupts (INTR and NMI), STPCLK
does not initiate interrupt acknowledge cycles or interrupt table
reads.
5.2.1
In write-through mode, the priority order of external in-
terrupts is:
External Interrupts in Order of Priority
1)
2)
3)
4)
5)
6)
RESET/SRESET
FLUSH
SMI
NMI
INTR
STPCLK
In write-back mode, the priority order of external inter-
rupts is:
1)
2)
3)
4)
5)
6)
7)
RESET
FLUSH
SRESET
SMI
NMI
INTR
STPCLK
STPCLK is active Low and has an internal pull-up re-
sistor. STPCLK is asynchronous, but setup and hold
times must be met to ensure recognition in any specific
clock. STPCLK must remain active until the Stop Grant
special bus cycle is asserted and the system responds
with either RDY or BRDY. When the CPU enters the
Stop Grant state, the internal pull-up resistor is disabled,
reducing the CPU power consumption. The STPCLK
input must be driven High (not floated) to exit the Stop
Grant state. STPCLK must be deasserted for a mini-
mum of five clocks after RDY or BRDY is returned active
for the Stop Grant bus cycle before being asserted
again. There are two regions for the low-power mode
supply current:
1)
Low Power: Stop Grant state (fast wake-up, frequency-
and voltage-dependent),
2)
Lowest Power: Stop Clock state (slow wake-up, voltage-
dependent).
5.3
The processor drives a special Stop Grant bus cycle to the
bus after recognizing the STPCLK interrupt. This bus cycle
is the same as the HALT cycle used by a standard Am486
microprocessor, with the exception that the Stop Grant bus
cycle drives the value 0000 0010h on the address pins.
Stop Grant Bus Cycle
n
M/lO = 0
n
D/C = 0
n
W/R =1
n
Address Bus = 0000 0010h (A
4
= 1)
n
BE3–BE0 = 1011
n
Data bus = undefined
The system hardware must acknowledge this cycle by re-
turning RDY or BRDY, or the processor will not enter the
Stop Grant state (see Figure 19). The latency between a
STPCLK request and the Stop Grant bus cycle depends on
the current instruction, the amount of data in the CPU write
buffers, and the system memory performance
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