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| 型号： | Enhanced Am486 dx4 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能设计片上集成完全32位体系微处理器) |
| 中文描述： | 高性能设计的片上集成完整的32位架构Micrprocessor（高性能设计片上集成完全32位体系微处理器） |
| 文件页数： | 55/69页 |
| 文件大小： | 1068K |
| 代理商： | ENHANCED AM486 DX4 |
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Enhanced Am486 Microprocessor
AMD
55
PRELIMINARY
n
Control (bits 1–0): Read/Write, independent of write-
through or write-back mode. The control bits deter-
mine which operation to performed. The following is
a definition of the control operations:
— 00 = Write to cache fill buffer, or read from cache
read buffer.
— 01 = Perform cache write.
— 10 = Perform cache read.
— 11 = Flush the cache (mark all entries invalid)
8.3
The following paragraphs provide examples of testing
the cache using TR4 and TR5.
Using TR4 and TR5 for Cache Testing
8.3.1
Example 1: Reading The Cache (write-back
mode only)
Disable caching by setting the CD bit in the CR0 reg-
ister.
In TR5, load 0 into the Ext field (bit 19), the required
index into the Index field (bits 10–4), the required entry
value into the Entry field (bits 3–2), and 10 into the
Control field (bits 1–0). Loading the values into TR5
triggers the cache read. The cache read loads the TR4
register with the TAG for the read entry, and the LRU
and Valid bits for the entire set that was read. The
cache read loads 128 data bits into the cache read
buffer. The entire buffer can be read by placing each
of the four binary combinations in the Entry field and
setting the Control field in TR5 to 00 (binary). Read
each doubleword from the cache read buffer through
TR3.
Reading the Set State fields in TR4 during write-back
mode is accomplished by setting the Ext field in TR5
to 1 and re-reading TR4.
8.3.2
Example 2: Writing The Cache
1)
Disable the cache by setting the CD bit in the CR0
register.
2)
In TR5, load 0 into the Ext field (bit 19), the required
entry value into the Entry field (bits 3–2), and 00 into
the Control field (bits 1–0).
3)
Load the TR3 register with the data to write to the cache
fill buffer. The cache fill buffer write is triggered by load-
ing TR3.
4)
Repeat steps 2 and 3 for the remaining three double-
words in the cache fill buffer.
5)
In TR4, load the required values into TAG field (bits 31–
11) and the Valid field (bit 10). In write-back mode, the
Valid bit is ignored since the Set State field in TR5 is
used in place of the TR4 Valid bit. The other bits in TR4
(9:0) have no effect on the cache write.
1)
2)
3)
6)
In TR5, load 0 into the Ext field (bit 19), the required
value into the Set State field (bits 18–17) (write-back
mode only), the required index into the Index field (bits
10–4), the required entry value into the Entry field (bits
3–2), and 01 into the Control field (bits 1–0). Loading
the values into TR5 triggers the cache write. In write-
write-through mode, the Set State field is ignored, and
the Valid bit (bit 10) in TR4 is used instead to define
the state of the specified set.
8.3.3
Example 3: Flushing The Cache
The cache flush mechanism functions in the same way
in write-back and write-through modes. Load 11 into
the Control field (bits 1–0) of TR5. All other fields are
ignored, except for Ext in write-back mode. The cache
flush is triggered by loading the value into TR5. All of
the LRU bits, Valid bits, and Set State bits are cleared.
9
Enhanced Am486 CPU Functional
Differences
Several important differences exist between the En-
hanced Am486 microprocessor and the Am486DX mi-
croprocessor:
n
The ID register contains a different version signa-
ture.
n
The EADS function performs cache line write-backs of
modified lines to memory in write-back mode.
n
A burst write feature is available for copy-backs. The
FLUSH pin and WBINVD instruction copy-back all mod-
ified data to external memory prior to issuing the special
bus cycle or reset.
9.1
Status after Reset
The RESET state is invoked either after power up or
after the RESET signal is applied according to the stan-
dard Am486DX microprocessor specification.
9.2
After reset, the STATUS bits of all lines are set to 0. The
LRU bits of each set are placed in a starting state.
Cache Status
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