- 您现在的位置：买卖IC网 > PDF目录362733 > Enhanced Am486 dx4 (Advanced Micro Devices, Inc.) High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能设计片上集成完全32位体系微处理器) PDF资料下载
参数资料
| 型号： | Enhanced Am486 dx4 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能设计片上集成完全32位体系微处理器) |
| 中文描述： | 高性能设计的片上集成完整的32位架构Micrprocessor（高性能设计片上集成完全32位体系微处理器） |
| 文件页数： | 44/69页 |
| 文件大小： | 1068K |
| 代理商： | ENHANCED AM486 DX4 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页当前第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页
Enhanced Am486 Microprocessor
AMD
Entering System Management Mode
SMM is one of the major operating modes, along with
Protected mode, Real mode, and Virtual mode. Figure
27 shows how the processor can enter SMM from any
of the three modes and then return.
44
PRELIMINARY
7.4
The external signal SMI causes the processor to switch to
SMM. The RSM instruction exits SMM. SMM is transparent
to applications programs and operating systems for the fol-
lowing reasons:
n
The only way to enter SMM is via a type of non-
maskable interrupt triggered by an external signal.
n
The processor begins executing SMM code from a
separate address space, referred to earlier as sys-
tem management RAM (SMRAM).
n
Upon entry into SMM, the processor saves the reg-
ister state of the interrupted program (depending on
the save mode) in a part of SMRAM called the SMM
context save space.
n
All interrupts normally handled by the operating sys-
tem or applications are disabled upon SMM entry.
n
A special instruction, RSM, restores processor reg-
isters from the SMM context save space and returns
control to the interrupted program.
Similar to Real mode, SMM has no privilege levels or
address mapping. SMM programs can execute all I/O
and other system instructions and can address up to 4
Gbytes of memory.
7.5
The RSM instruction (opcode 0F AAh) leaves SMM and
returns control to the interrupted program. The RSM
instruction can be executed only in SMM. An attempt to
execute the RSM instruction outside of SMM generates
an invalid opcode exception. When the RSM instruction
is executed and the processor detects invalid state in-
formation during the reloading of the save state, the
Exiting System Management Mode
Virtual
Mode
System
Management
Mode
Reset
Reset
or
RSM
SMI
RSM
RSM
VM=1
PE=1
Reset
or
PE=0
VM=0
Figure 27. Transition to and from SMM
Real
Mode
Protected
Mode
SMI
SMI
processor enters the shutdown state. This occurs in the
following situations:
n
The value in the State Dump base field is not a
32-Kbyte aligned address.
n
A combination of bits in CR0 is illegal: (PG=1 and
PE=0) or (NW=1 and CD=0).
In shutdown mode, the processor stops executing in-
structions until an NMI interrupt is received or reset ini-
tialization is invoked. The processor generates a
shutdown bus cycle.
Four SMM features can be enabled by writing to control
slots in the SMRAM state save area:
1)
Auto
HALT Restart
. It is possible for the SMI request
to interrupt the HALT state. The SMI handler can tell the
RSM instruction to return control to the HALT instruction
or to return control to the instruction following the HALT
instruction by appropriately setting the Auto HALT Re-
start slot. The default operation is to restart the HALT
instruction.
I/O Trap Restart
. If the SMI was generated on an I/O
access to a powered-down device, the SMI handler
can instruct the RSM instruction to re-execute that I/O
instruction by setting the I/O Trap Restart slot.
SMBASE Relocation
. The system can relocate the
SMRAM by setting the SMBASE Relocation slot in the
state save area. The RSM instruction sets SMBASE
in the processor based on the value in the SMBASE
relocation slot. The SMBASE must be aligned on 32-
Kbyte boundaries.
A RESET also causes execution to exit from SMM.
2)
3)
7.6
When an SMI signal is recognized on an instruction execution
boundary, the processor waits for all stores to complete, in-
cluding emptying the write buffers. The final write cycle is com-
plete when the system returns RDY or BRDY. The processor
then drives SMIACT active, saves its register state to SMRAM
space, and begins to execute the SMI handler.
Processor Environment
SMI has greater priority than debug exceptions and external
interrupts. This means that if more than one of these condi-
tions occur at an instruction boundary, only the SMI processing
occurs. Subsequent SMI requests are not acknowledged
while the processor is in SMM. The first SMI request that oc-
curs while the processor is in SMM is latched, and serviced
when the processor exits SMM with the RSM instruction. Only
one SMI signal is latched by the CPU while it is in SMM. When
the CPU invokes SMM, the CPU core registers are initialized
as indicated in Table 11.
相关PDF资料 |
PDF描述 |
|---|---|
| EO12 | IRDA INFRARED TRANSCEIVER |
| EOL-62L256 | HT62L256 EOL Notification |
| EP05FA20 | FRD |
| EP05Q03L | SBD |
| EP05Q06 | SBD Type : EP05Q06 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ENHSAURR8 | 制造商:Molex 功能描述:8 PORT MACHINE MOUNT SWITCH 制造商:Molex 功能描述:COMPUTERS, NETWORK SWITCHES CONNECTIVITY, No. of Ports:8, Data Rate Max:100Mbps, |
| ENHSDURR5 | 制造商:Molex 功能描述:COMPUTERS, NETWORK SWITCHES CONNECTIVITY, No. of Ports:5, Switch Mounting:DIN Ra 制造商:Molex 功能描述:ETHERNET DIN RAIL SWITCH 5PORT |
| ENHSDURR9 | 制造商:MOLEX/WOODHEAD 功能描述:Ethernet Network Switch 制造商:Molex 功能描述:ETHERNET NETWORK SWITCH, No. of Ports:9, Data Rate Max:100Mbps, Switch Mounting: |
| ENI-110 | 功能描述:冲压机与冲模 NON-IMPACT PUNCHDOWN TOOL RoHS:否 制造商:Souriau 大小: 产品:Dies 类型:Crimping 描述/功能: |
| ENICSF2811PBKA | 制造商:Texas Instruments 功能描述: |
发布紧急采购，3分钟左右您将得到回复。