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参数资料
| 型号： | Enhanced Am486 dx4 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能设计片上集成完全32位体系微处理器) |
| 中文描述： | 高性能设计的片上集成完整的32位架构Micrprocessor（高性能设计片上集成完全32位体系微处理器） |
| 文件页数： | 18/69页 |
| 文件大小： | 1068K |
| 代理商： | ENHANCED AM486 DX4 |
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Enhanced Am486 Microprocessor
AMD
18
PRELIMINARY
4.3.3
Protected Mode provides access to the sophisticated
memory management paging and privilege capabilities
of the processor.
Protected Mode
4.3.4
SMM is a special operating mode described in detail in
Section 7.
System Management Mode
4.4
The Enhanced Am486 microprocessor family supports
a superset architecture of the standard 486 cache im-
plementation. This architectural enhancement im-
proves not only CPU performance, but total system
performance.
Cache Architecture
4.4.1
The standard 486DX-type write-through cache architec-
ture is characterized by the following:
Write-Through Cache
n
External read accesses are placed in the cache if
they meet proper caching requirements.
n
Subsequent reads to the data in the cache are made
if the address is stored in the cache tag array.
n
Write operations to a valid address in the cache are
updated in the cache andto external memory. This
data writing technique is called write-through
The write-through cache implementation forces all
writes to flow through to the external bus and back to
main memory. Consequently, the write-through cache
generates a large amount of bus traffic on the external
data bus.
4.4.2
The microprocessor write-back cache architecture is
characterized by the following:
Write-Back Cache
n
External read accesses are placed in the cache if
they meet proper caching requirements.
n
Subsequent reads to the data in the cache are made
if the address is stored in the cache tag array.
n
Write operations to a valid address in the cache that
is in the write-through (shared) state is updated in
the cache and to external memory.
n
Write operations to a valid address in the cache that
is in the write-back (exclusive or modified) state is
updated only in the cache. External memory is not
updated at the time of the cache update.
n
Modified data is written back to external memory
when the modified cache line is being replaced with
a new cache line (copy-back operation) or an exter-
nal bus master has snooped a modified cache line
(write-back).
The write-back cache feature significantly reduces the
amount of bus traffic on the external bus; however, it
also adds complexity to the system design to maintain
4
4.1
Enhanced Am486 microprocessors use a 32-bit archi-
tecture with on-chip memory management and cache
memory units. The instruction set includes the complete
486 microprocessor instruction set along with exten-
sions to serve the new extended applications. All soft-
ware written for the 486 microprocessor and previous
members of the X86 architectural family can run on the
Enhanced Am486 microprocessor without modification.
FUNCTIONAL DESCRIPTION
Overview
The on-chip Memory Management Unit (MMU) is com-
pletely compatible with the 486 MMU. The MMU in-
cludes a segmentation unit and a paging unit. Segmentation
allows management of the logical address space by pro-
viding easy data and code relocatibility and efficient sharing
of global resources. The paging mechanism operates be-
neath segmentation and is transparent to the segmentation
process. Paging is optional and can be disabled by system
software. Each segment can be divided into one or more
4-Kbyte segments. To implement a virtual memory system,
the Enhanced Am486 microprocessor supports full restart-
ability for all page and segment faults.
4.2
Memory is organized into one or more variable length
segments, each up to 4 Gbytes (2
32
bytes). A segment
can have attributes associated with it, including its location,
size, type (i.e., stack, code, or data), and protection charac-
teristics. Each task on a microprocessor can have a maxi-
mum of 16,381 segments, each up to 4 Gbytes. Thus, each
task has a maximum of 64 Tbytes of virtual memory.
Memory
The segmentation unit provides four levels of protection
for isolating and protecting applications and the operat-
ing system from each other. The hardware-enforced
protection allows high integrity system designs.
4.3
The Enhanced Am486 microprocessor has four modes
of operation: Real Address Mode (Real Mode), Virtual
8086 Address Mode (Virtual Mode), Protected Address
Mode (Protected Mode), and System Management
Mode (SMM).
Modes of Operation
4.3.1
In Real Mode, the Enhanced Am486 microprocessor
operates as a fast 8086. Real Mode is required primarily
to set up the processor for Protected Mode operation.
Real Mode
4.3.2
In Virtual Mode, the processor appears to be in Real
Mode, but can use the extended memory accessing of
Protected Mode.
Virtual Mode
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