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| 型号： | Enhanced Am486 dx4 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能设计片上集成完全32位体系微处理器) |
| 中文描述： | 高性能设计的片上集成完整的32位架构Micrprocessor（高性能设计片上集成完全32位体系微处理器） |
| 文件页数： | 6/69页 |
| 文件大小： | 1068K |
| 代理商： | ENHANCED AM486 DX4 |
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AMD
6
PRELIMINARY
Enhanced Am486 Microprocessor
8
Test Registers 4 and 5 Modifications ..................................................................................................53
8.1 TR4 Definition................................................................................................................................53
8.2 TR5 Definition................................................................................................................................54
8.3 Using TR4 and TR5 for Cache Testing..........................................................................................55
8.3.1 Example 1: Reading the Cache (write-back mode only) ......................................................55
8.3.2 Example 2: Writing the Cache..............................................................................................55
8.3.3 Example 3: Flushing the Cache ...........................................................................................55
Enhanced Am486 CPU Functional Differences ..................................................................................55
9.1 Status after Reset .........................................................................................................................55
9.2 Cache Status ................................................................................................................................55
10 Enhanced Am486 CPU Identification ..................................................................................................56
10.1 DX Register at RESET ................................................................................................................56
10.2 CPUID Instruction .......................................................................................................................56
10.2.1 CPUID Timing ...................................................................................................................56
10.2.2 CPUID Operation ..............................................................................................................56
11 Electrical Data .....................................................................................................................................57
11.1 Power and Grounding .................................................................................................................57
11.1.1 Power Connections ...........................................................................................................57
11.1.2 Power Decoupling Recommendations ..............................................................................57
11.1.3 Other Connection Recommendations ...............................................................................57
12 Package Thermal Specifications .........................................................................................................67
13 Physical Dimensions ...........................................................................................................................68
9
FIGURES
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10 Valid HOLD Assertion During Write-Back ...............................................................................27
Figure 11 Closely Coupled Cache Block Diagram ..................................................................................28
Figure 12 Snoop Hit Cycle with Write-Back .............................................................................................29
Figure 13 Cycle Reordering with BOFF (Write-Back) ..............................................................................30
Figure 14 Write Reordering Due to Buffering ..........................................................................................31
Figure 15 Latest Snooping of Copy-Back ................................................................................................33
Figure 16 Burst Write ..............................................................................................................................34
Figure 17 Burst Read with BOFF Assertion ............................................................................................34
Figure 18 Burst Write with BOFF Assertion .............................................................................................35
Figure 19 Entering Stop Grant State .......................................................................................................37
Figure 20 Recognition of Inputs when Exiting Stop Grant State .............................................................38
Figure 21 Stop Clock State Machine .......................................................................................................38
Figure 22 Basic SMI Interrupt Service .....................................................................................................40
Figure 23 Basic SMI Hardware Interface..................................................................................................41
Figure 24 SMI Timing for Servicing an I/O Trap ......................................................................................41
Figure 25 SMIACT Timing .......................................................................................................................42
Figure 26 Redirecting System Memory Address to SMRAM ...................................................................42
Figure 27 Transition to and from SMM ....................................................................................................44
Figure 28 Auto HALT Restart Register Offset..........................................................................................47
Figure 29 I/O Instruction Restart Register Offset ....................................................................................47
Processor-Induced Line Transitions in Write-Back Mode .......................................................20
Snooping State Transitions .....................................................................................................21
Typical System Block Diagram for HOLD/HLDA Bus Arbitration ............................................22
External Read .........................................................................................................................23
External Write ..........................................................................................................................23
Snoop of On-Chip Cache That Does Not Hit a Line ................................................................24
Snoop of On-Chip Cache That Hits a Non-modified Line ........................................................24
Snoop That Hits a Modified Line (Write-Back) ........................................................................25
Write-Back and Pending Access .............................................................................................26
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