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| 型号： | Enhanced Am486 dx4 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | High-Performance Design On-Chip Integration Complete 32-Bit Architecture Micrprocessor(高性能设计片上集成完全32位体系微处理器) |
| 中文描述： | 高性能设计的片上集成完整的32位架构Micrprocessor（高性能设计片上集成完全32位体系微处理器） |
| 文件页数： | 45/69页 |
| 文件大小： | 1068K |
| 代理商： | ENHANCED AM486 DX4 |
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Enhanced Am486 Microprocessor
AMD
45
PRELIMINARY
Note
:
Interrupts from INT and NMI are disabled on SMM entry.
The following is a summary of the key features in the
SMM environment:
n
Real mode style address calculation
n
4-Gbyte limit checking
n
IF flag is cleared
n
NMI is disabled
n
TF flag in EFLAGS is cleared; single step traps are
disabled
n
DR7 is cleared; debug traps are disabled
n
The RSM instruction no longer generates an invalid
op code error
n
Default 16-bit op code, register, and stack use.
n
All bus arbitration (HOLD, AHOLD, BOFF) inputs, and
bus sizing (BS8, BS16) inputs operate normally while the
CPU is in SMM.
7.7
Executing System Management
Mode Handler
The processor begins execution of the SMI handler at
offset 8000h in the CS segment. The CS Base is initially
30000h, as shown in Table 12.
Table 11. SMM Initial CPU Core Register Settings
Register
SMM Initial State
General Purpose
Registers
Unmodified
EFLAGS
0000 0002h
CR0
Bits 0, 2, 3, and 31 cleared (PE, EM, TS,
and PG); rest unmodified
DR6
Unpredictable state
DR7
0000 0400h
GDTR, LDTR,
IDTR, TSSR
Unmodified
EIP
0000 8000h
Notes
:
1. The segment limit check is 4 Gbytes instead of the usual 64K.
2. The Selector value for CS remains at 3000h even if the SMBASE
is changed.
The CS Base can be changed using the SMM Base relo-
cation feature. When the SMI handler is invoked, the
CPU’s PE and PG bits in CR0 are reset to 0. The pro-
cessor is in an environment similar to Real mode, but
without the 64-Kbyte limit checking. However, the de-
fault operand size and the default address size are set
to 16 bits. The EM bit is cleared so that no exceptions
are generated. (If the SMM was entered from Protected
mode, the Real mode interrupt and exception support
is not available.) The SMI handler should not use float-
ing-point unit instructions until the FPU is properly de-
tected (within the SMI handler) and the exception
support is initialized.
Because the segment bases (other than CS) are
cleared to 0 and the segment limits are set to 4 Gbytes,
the address space may be treated as a single flat
4-Gbyte linear space that is unsegmented. The CPU is
still in Real mode and when a segment selector is loaded
with a 16-bit value, that value is then shifted left by 4
bits and loaded into the segment base cache.
In SMM, the CPU can access or jump anywhere within
the 4-Gbyte logical address space. The CPU can also
indirectly access or perform a near jump anywhere with-
in the 4-Gbyte logical address space.
Table 12. Segment Register Initial States
Segment
Register
Selector
Base
Attributes
Limit
1
CS
2
3000h
30000h
16-bit,
expand up
16-bit,
expand up
16-bit,
expand up
16-bit,
expand up
16-bit,
expand up
16-bit,
expand up
4 Gbytes
DS
0000h
00000000h
4 Gbytes
ES
0000h
00000000h
4 Gbytes
FS
0000h
00000000h
4 Gbytes
GS
0000h
00000000h
4 Gbytes
SS
0000h
00000000h
4 Gbytes
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