参数资料
型号: EP20K60EFC484-2
厂商: ALTERA CORP
元件分类: PLD
英文描述: LOADABLE PLD, PBGA484
封装: 23 X 23 MM, 1 MM PITCH, FINE LINE, BGA-484
文件页数: 50/114页
文件大小: 4116K
代理商: EP20K60EFC484-2
IGLOO nano DC and Switching Characteristics
2- 26
Advance v0.2
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-35 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tPYS
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
STD
0.97
3.94
0.19
0.85
1.14
0.66
3.39
2.95
1.82
1.87
ns
4 mA
STD
0.97
3.94
0.19
0.85
1.14
0.66
3.39
2.95
1.82
1.87
ns
6 mA
STD
0.97
3.20
0.19
0.85
1.14
0.66
2.88
2.65
2.04
2.27
ns
8 mA
STD
0.97
3.20
0.19
0.85
1.14
0.66
2.88
2.65
2.04
2.27
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-36 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Drive Strength
Speed Grade
tDOUT
tDP
tDIN
tPY
tPYS
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
STD
0.97
2.35
0.19
0.85
1.14
0.66
1.88
1.43
1.81
1.98
ns
4 mA
STD
0.97
2.35
0.19
0.85
1.14
0.66
1.88
1.43
1.81
1.98
ns
6 mA
STD
0.97
1.96
0.19
0.85
1.14
0.66
1.73
1.32
2.04
2.38
ns
8 mA
STD
0.97
1.96
0.19
0.85
1.14
0.66
1.73
1.32
2.04
2.38
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
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