参数资料
型号: EP20K60EFC484-2
厂商: ALTERA CORP
元件分类: PLD
英文描述: LOADABLE PLD, PBGA484
封装: 23 X 23 MM, 1 MM PITCH, FINE LINE, BGA-484
文件页数: 78/114页
文件大小: 4116K
代理商: EP20K60EFC484-2
IGLOO nano DC and Switching Characteristics
2- 52
Advance v0.2
1.2 V DC Core Voltage
Table 2-75 Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC =1.14V
Parameter
Description
Std.
Units
tDDROCLKQ
Clock-to-Out of DDR for Output DDR
1.60
ns
tDDROSUD1
Data_F Data Setup for Output DDR
1.09
ns
tDDROSUD2
Data_R Data Setup for Output DDR
1.16
ns
tDDROHD1
Data_F Data Hold for Output DDR
0.00
ns
tDDROHD2
Data_R Data Hold for Output DDR
0.00
ns
tDDROCLR2Q
Asynchronous Clear-to-Out for Output DDR
1.99
ns
tDDROREMCLR
Asynchronous Clear Removal Time for Output DDR
0.00
ns
tDDRORECCLR
Asynchronous Clear Recovery Time for Output DDR
0.24
ns
tDDROWCLR1
Asynchronous Clear Minimum Pulse Width for Output DDR
0.19
ns
tDDROCKMPWH
Clock Minimum Pulse Width HIGH for the Output DDR
0.31
ns
tDDROCKMPWL
Clock Minimum Pulse Width LOW for the Output DDR
0.28
ns
FDDOMAX
Maximum Frequency for the Output DDR
TBD
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating
values.
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