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参数资料
型号： EP2C20F256I6N
厂商： ALTERA CORP
元件分类： FPGA
英文描述： FPGA, 1196 CLBS, PBGA256
封装： LEAD FREE, FBGA-256
文件页数： 143/168页
文件大小： 2206K
代理商： EP2C20F256I6N
3–2
Altera Corporation
Cyclone II Device Handbook, Volume 1
February 2007
IEEE Std. 1149.1 (JTAG) Boundary Scan Support
Cyclone II devices also use the JTAG port to monitor the logic operation
of the device with the SignalTap II embedded logic analyzer. Cyclone II
devices support the JTAG instructions shown in Table 3–1.
Table 3–1. Cyclone II JTAG Instructions (Part 1 of 2)
JTAG Instruction
Instruction Code
Description
SAMPLE/PRELOAD
00 0000 0101
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial
data pattern to be output at the device pins. Also used by the
SignalTap II embedded logic analyzer.
EXTEST (1)
00 0000 1111
Allows the external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
BYPASS
11 1111 1111
Places the 1-bit bypass register between the
TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation.
USERCODE
00 0000 0111
Selects the 32-bit
USERCODE register and places it between the
TDI and TDO pins, allowing the USERCODE to be serially shifted
out of
TDO.
IDCODE
00 0000 0110
Selects the
IDCODE register and places it between TDI and TDO,
allowing the
IDCODE to be serially shifted out of TDO.
HIGHZ (1)
00 0000 1011
Places the 1-bit bypass register between the
TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation, while
tri-stating all of the I/O pins.
CLAMP (1)
00 0000 1010
Places the 1-bit bypass register between the
TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation while
holding I/O pins to a state defined by the data in the boundary-scan
register.
ICR
instructions
Used when configuring a Cyclone II device via the JTAG port with
a USB Blaster, ByteBlaster II, MasterBlaster or
ByteBlasterMV download cable, or when using a Jam File or JBC
File via an embedded processor.
PULSE_NCONFIG
00 0000 0001
Emulates pulsing the
nCONFIG pin low to trigger reconfiguration
even though the physical pin is unaffected.
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相关代理商/技术参数
参数描述
EP2C20F256I8 功能描述:FPGA - 现场可编程门阵列 FPGA - Cyclone II 1172 LABs 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP2C20F256I8GA 制造商:Altera Corporation 功能描述:
EP2C20F256I8N 功能描述:FPGA - 现场可编程门阵列 FPGA - Cyclone II 1172 LABs 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP2C20F484C6 功能描述:FPGA - 现场可编程门阵列 FPGA - Cyclone II 1172 LABs 315 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP2C20F484C6N 功能描述:FPGA - 现场可编程门阵列 FPGA - Cyclone II 1172 LABs 315 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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