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型号： HW-SPAR3AN-SK-UNI-G
厂商： Xilinx Inc
文件页数： 128/140页
文件大小： 0K
描述： KIT STARTER SPARTAN-3 AN
产品变化通告： Adapter Replacement 23/May/2008
标准包装： 1
系列： Spartan®-3AN
类型： FPGA
适用于相关产品： Spartan-3AN XC3S700AN-FG484，XCF04S-VOG20C
所含物品： 面板、缆线、软件、数据表和用户手册
相关产品： XC3S700AN-5FGG484C-ND - IC FPGA SPARTAN-3A 700K 484-FBGA
122-1598-ND - IC FPGA SPARTAN -3AN700K 484FBGA
122-1556-ND - IC SPARTAN-3AN FPGA 700K 484FBGA
其它名称： 122-1528
HW-SPAR3AN-SK-UNI-G-PROMO
HW-SPAR3AN-SK-UNI-G-PROMO-ND
Chapter 15: Expansion Connectors
34-Conductor Cable Assemblies (2x17)
The J2 and J15 headers were designed specifically to connect to 34-conductor flat ribbon
cable assemblies that use a 2x17, 0.1-inch form factor.
R
Table 15-5:
Example 34-Conductor Cable Assemblies
Distributor
Digi-Key
www.digikey.com
Manufacturer
3M
CW Industries
CW Industries
Distributor
Part Number
M3AAK-3420K-ND
C3AAG-3406G-ND
C3AAG-3406M-ND
C3AAG-3418G-ND
C3AAG-3418M-ND
Type
Flat ribbon cable, multi-color, twisted
pair, gold finish
Flat ribbon cable, gray, gold finish
Flat ribbon cable, multi-color, gold finish
Flat ribbon cable, gray, gold finish
Flat ribbon cable, multi-color, gold finish
Length
50.80 cm
(20 inch)
15.24 cm
(6 inch)
45.72 cm
(18 inch)
UCF Location Constraints
Figure 15-7 provides the User Constraint File (UCF) constraints for the “Receive” and
“Transmit” headers, including the I/O pin assignment and the I/O standard used.
# High-Speed LVDS “Receive”
Connector (RX)
NET "RX_CLK_N" LOC = "A11"
NET "RX_CLK_P" LOC = "A12"
| IOSTANDARD =
| IOSTANDARD =
LVDS_33
LVDS_33
;
;
NET "RX_N<0>"
NET "RX_P<0>"
NET "RX_N<1>"
NET "RX_P<1>"
NET "RX_N<2>"
NET "RX_P<2>"
NET "RX_N<3>"
NET "RX_P<3>"
NET "RX_N<4>"
NET "RX_P<4>"
LOC = "B4"
LOC = "A4"
LOC = "A5"
LOC = "B6"
LOC = "A6"
LOC = "A7"
LOC = "A8"
LOC = "A9"
LOC = "C10"
LOC = "A10"
| IOSTANDARD =
| IOSTANDARD =
| IOSTANDARD =
| IOSTANDARD =
| IOSTANDARD =
| IOSTANDARD =
| IOSTANDARD =
| IOSTANDARD =
| IOSTANDARD =
| IOSTANDARD =
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
LVDS_33
;
;
;
;
;
;
;
;
;
;
# High-Speed LVDS “Transmit” Connector (TX)
NET "TX_CLK_N" LOC = "AB10" | IOSTANDARD = LVDS_33
NET "TX_CLK_P" LOC = "AA10" | IOSTANDARD = LVDS_33
;
;
NET "TX_N<0>"
NET "TX_P<0>"
NET "TX_N<1>"
NET "TX_P<1>"
NET "TX_N<2>"
NET "TX_P<2>"
NET "TX_N<3>"
NET "TX_P<3>"
NET "TX_N<4>"
NET "TX_P<4>"
LOC = "AA3" | IOSTANDARD = LVDS_33
LOC = "AB2" | IOSTANDARD = LVDS_33
LOC = "AA4" | IOSTANDARD = LVDS_33
LOC = "AB3" | IOSTANDARD = LVDS_33
LOC = "AB6" | IOSTANDARD = LVDS_33
LOC = "AA6" | IOSTANDARD = LVDS_33
LOC = "AB7" | IOSTANDARD = LVDS_33
LOC = "Y7" | IOSTANDARD = LVDS_33
LOC = "AB8" | IOSTANDARD = LVDS_33
LOC = "AA8" | IOSTANDARD = LVDS_33
;
;
;
;
;
;
;
;
;
;
Figure 15-7: UCF Location Constraints for “Receive” and “Transmit” Headers
128
www.xilinx.com Spartan-3A/3AN FPGA Starter Kit Board User Guide
UG334 (v1.1) June 19, 2008
相关PDF资料
PDF描述
HW-V4-ML403-UNI-G-J EVALUATION PLATFORM VIRTEX-4
HW-V4-ML405-UNI-G-J EVALUATION PLATFORM VIRTEX-4
HW-V4-ML410-UNI-G-J EVALUATION PLATFORM VIRTEX-4
HW-V5-ML501-UNI-G EVALUATION PLATFORM VIRTEX-5
HW-V5-ML507-UNI-G EVAL PLATFORM V5 FXT
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