参数资料
型号: HW-SPAR3AN-SK-UNI-G
厂商: Xilinx Inc
文件页数: 61/140页
文件大小: 0K
描述: KIT STARTER SPARTAN-3 AN
产品变化通告: Adapter Replacement 23/May/2008
标准包装: 1
系列: Spartan®-3AN
类型: FPGA
适用于相关产品: Spartan-3AN XC3S700AN-FG484,XCF04S-VOG20C
所含物品: 面板、缆线、软件、数据表和用户手册
相关产品: XC3S700AN-5FGG484C-ND - IC FPGA SPARTAN-3A 700K 484-FBGA
122-1598-ND - IC FPGA SPARTAN -3AN700K 484FBGA
122-1556-ND - IC SPARTAN-3AN FPGA 700K 484FBGA
其它名称: 122-1528
HW-SPAR3AN-SK-UNI-G-PROMO
HW-SPAR3AN-SK-UNI-G-PROMO-ND
R
UCF Location Constraints
A separate counter tracks the vertical timing. The vertical-sync counter increments with
each HS pulse, and decoded values generate the VS signal. This counter tracks the current
display row. These two continuously running counters form the address into a video
display buffer. For example, the on-board DDR2 SDRAM provides an ideal display buffer.
No time relationship is specified between the onset of the HS pulse and the onset of the VS
pulse. Consequently, the counters can be arranged to easily form video RAM addresses or
to minimize decoding logic for sync pulse generation.
UCF Location Constraints
Figure 6-4 provides the UCF constraints for the VGA display port, including the I/O pin
assignment, the I/O standard used, the output slew rate, and the output drive current.
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"VGA_R<3>"
"VGA_R<2>"
"VGA_R<1>"
"VGA_R<0>"
"VGA_G<3>"
"VGA_G<2>"
"VGA_G<1>"
"VGA_G<0>"
"VGA_B<3>"
"VGA_B<2>"
"VGA_B<1>"
"VGA_B<0>"
LOC = "C8"
LOC = "B8"
LOC = "B3"
LOC = "A3"
LOC = "D6"
LOC = "C6"
LOC = "D5"
LOC = "C5"
LOC = "C9"
LOC = "B9"
LOC = "D7"
LOC = "C7"
|
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|
|
|
|
|
|
|
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IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
=
=
=
=
=
=
=
=
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
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|
|
|
|
|
|
|
|
|
|
|
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
DRIVE
=
=
=
=
=
=
=
=
=
=
=
=
8
8
8
8
8
8
8
8
8
8
8
8
|
|
|
|
|
|
|
|
|
|
|
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SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
=
=
=
=
=
=
=
=
=
=
=
=
FAST
FAST
FAST
FAST
FAST
FAST
FAST
FAST
FAST
FAST
FAST
FAST
;
;
;
;
;
;
;
;
;
;
;
;
NET
NET
"VGA_HSYNC" LOC = "C11"
"VGA_VSYNC" LOC = "B11"
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|
IOSTANDARD
IOSTANDARD
=
=
LVCMOS33
LVCMOS33
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|
DRIVE
DRIVE
=
=
8
8
|
|
SLEW
SLEW
=
=
FAST
FAST
;
;
Figure 6-4: UCF Constraints for VGA Display Port
Related Resources
Refer to the following links for additional information:
?
?
VESA
VGA timing information
Spartan-3A/3AN FPGA Starter Kit Board User Guide www.xilinx.com
UG334 (v1.1) June 19, 2008
61
相关PDF资料
PDF描述
HW-V4-ML403-UNI-G-J EVALUATION PLATFORM VIRTEX-4
HW-V4-ML405-UNI-G-J EVALUATION PLATFORM VIRTEX-4
HW-V4-ML410-UNI-G-J EVALUATION PLATFORM VIRTEX-4
HW-V5-ML501-UNI-G EVALUATION PLATFORM VIRTEX-5
HW-V5-ML507-UNI-G EVAL PLATFORM V5 FXT
相关代理商/技术参数
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