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型号： HW-SPAR3AN-SK-UNI-G
厂商： Xilinx Inc
文件页数： 88/140页
文件大小： 0K
描述： KIT STARTER SPARTAN-3 AN
产品变化通告： Adapter Replacement 23/May/2008
标准包装： 1
系列： Spartan®-3AN
类型： FPGA
适用于相关产品： Spartan-3AN XC3S700AN-FG484，XCF04S-VOG20C
所含物品： 面板、缆线、软件、数据表和用户手册
相关产品： XC3S700AN-5FGG484C-ND - IC FPGA SPARTAN-3A 700K 484-FBGA
122-1598-ND - IC FPGA SPARTAN -3AN700K 484FBGA
122-1556-ND - IC SPARTAN-3AN FPGA 700K 484FBGA
其它名称： 122-1528
HW-SPAR3AN-SK-UNI-G-PROMO
HW-SPAR3AN-SK-UNI-G-PROMO-ND
Chapter 11: Parallel NOR Flash PROM
Data
Figure 11-3 provides the UCF constraints for the Flash data pins, including the I/O pin
assignment and the I/O standard used.
R
# NET "NF_D<15>" -->
use NF_A<0> on pin T17 when NF_BYTE =
High
NET "NF_D<14>" LOC =
NET "NF_D<13>" LOC =
NET "NF_D<12>" LOC =
NET "NF_D<11>" LOC =
NET "NF_D<10>" LOC =
"R21" | IOSTANDARD = LVCMOS33 | DRIVE
"T22" | IOSTANDARD = LVCMOS33 | DRIVE
"U22" | IOSTANDARD = LVCMOS33 | DRIVE
"U21" | IOSTANDARD = LVCMOS33 | DRIVE
"V22" | IOSTANDARD = LVCMOS33 | DRIVE
= 8 |
= 8 |
= 8 |
= 8 |
= 8 |
SLEW
SLEW
SLEW
SLEW
SLEW
=
=
=
=
=
SLOW
SLOW
SLOW
SLOW
SLOW
;
;
;
;
;
NET "NF_D<9>"
NET "NF_D<8>"
NET "NF_D<7>"
NET "NF_D<6>"
NET "NF_D<5>"
NET "NF_D<4>"
NET "NF_D<3>"
NET "NF_D<2>"
NET "NF_D<1>"
LOC =
LOC =
LOC =
LOC =
LOC =
LOC =
LOC =
LOC =
LOC =
"W22" | IOSTANDARD = LVCMOS33 | DRIVE
"T20" | IOSTANDARD = LVCMOS33 | DRIVE
"Y9" | IOSTANDARD = LVCMOS33 | DRIVE
"AB9" | IOSTANDARD = LVCMOS33 | DRIVE
"Y11" | IOSTANDARD = LVCMOS33 | DRIVE
"AB11" | IOSTANDARD = LVCMOS33 | DRIVE
"U13" | IOSTANDARD = LVCMOS33 | DRIVE
"AA17" | IOSTANDARD = LVCMOS33 | DRIVE
"Y17" | IOSTANDARD = LVCMOS33 | DRIVE
= 8 |
= 8 |
= 8 |
= 8 |
= 8 |
= 8 |
= 8 |
= 8 |
= 8 |
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
SLEW
=
=
=
=
=
=
=
=
=
SLOW
SLOW
SLOW
SLOW
SLOW
SLOW
SLOW
SLOW
SLOW
;
;
;
;
;
;
;
;
;
NET "SPI_MISO" LOC =
"AB20" | IOSTANDARD = LVCMOS33 | DRIVE
= 8 |
SLEW
=
SLOW
;
Figure 11-3:
UCF Location Constraints for Flash Data I/O Pins
Control
Figure 11-4 provides the UCF constraints for the Flash control pins, including the I/O pin
assignment and the I/O standard used.
NET
NET
NET
NET
"NF_BYTE"
"NF_CE"
"NF_OE"
"NF_RP"
LOC
LOC
LOC
LOC
=
=
=
=
"Y21"
"W20"
"W19"
"R22"
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
LVCMOS33
LVCMOS33
LVCMOS33
LVCMOS33
|
|
|
|
DRIVE
DRIVE
DRIVE
DRIVE
=
=
=
=
8
8
8
8
|
|
|
|
SLEW
SLEW
SLEW
SLEW
=
=
=
=
SLOW
SLOW
SLOW
SLOW
;
;
;
;
NET
"NF_STS"
LOC
=
"P22"
|
IOSTANDARD
=
LVCMOS33
;
NET
NET
"NF_WE"
"NF_WP"
LOC
LOC
=
=
"AA22"
"E14"
|
|
IOSTANDARD
IOSTANDARD
=
=
LVCMOS33
LVCMOS33
|
|
DRIVE = 8 | SLEW = SLOW ;
DRIVE = 8 | SLEW = SLOW ;
Figure 11-4:
UCF Location Constraints for Flash Control Pins
Setting the FPGA Mode Select Pins
To configure the FPGA from NOR Flash, set the FPGA configuration mode pins for BPI Up
mode, as shown in Table 11-3 . The Spartan-3A/3AN FPGA families do not support the BPI
Down mode that is available in the Spartan-3E FPGA family.
Also be sure to disable the Platform Flash PROM by removing jumper J46, as shown in
Table 11-3 .
Table 11-3:
Selecting BPI-Up Configuration Mode (J26)
Configuration
Mode
BPI Up
Mode Pins
M2:M1:M0
0:1:0
FPGA Configuration Image in
Flash
FPGA starts at address 0 and
increments through address space.
Mode Select Jumper
Settings (J26)
M0
Platform Flash
Enable (J46)
DONE
M1
M2
J26
CE
PROM
GND
J46
88
www.xilinx.com Spartan-3A/3AN FPGA Starter Kit Board User Guide
UG334 (v1.1) June 19, 2008
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