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型号： HW-SPAR3AN-SK-UNI-G
厂商： Xilinx Inc
文件页数： 82/140页
文件大小： 0K
描述： KIT STARTER SPARTAN-3 AN
产品变化通告： Adapter Replacement 23/May/2008
标准包装： 1
系列： Spartan®-3AN
类型： FPGA
适用于相关产品： Spartan-3AN XC3S700AN-FG484，XCF04S-VOG20C
所含物品： 面板、缆线、软件、数据表和用户手册
相关产品： XC3S700AN-5FGG484C-ND - IC FPGA SPARTAN-3A 700K 484-FBGA
122-1598-ND - IC FPGA SPARTAN -3AN700K 484FBGA
122-1556-ND - IC SPARTAN-3AN FPGA 700K 484FBGA
其它名称： 122-1528
HW-SPAR3AN-SK-UNI-G-PROMO
HW-SPAR3AN-SK-UNI-G-PROMO-ND
Chapter 10: Digital-to-Analog Converter (DAC)
R
The FPGA first sends eight dummy or don’t care bits, followed by a four-bit command. The
most commonly used command with the board is COMMAND[3:0] = 0011 binary, which
immediately updates the selected DAC output with the specified data value. Following the
command, the FPGA selects one or all the DAC output channels via a four-bit address
field. Following the address field, the FPGA sends a 12-bit unsigned data value that the
DAC converts to an analog value on the selected output(s). Finally, four additional dummy
or don’t care bits pad the 32-bit command word.
Specifying the DAC Output Voltage
As shown in Figure 10-2 , each DAC output level is the analog equivalent of a 12-bit
unsigned digital value, D[11:0], written by the FPGA to the DAC via the SPI interface.
The voltage on a specific output is generally described in Equation 10-1 . The reference
voltage, V REFERENCE , is different between the four DAC outputs. Channels A and B use a
3.3V reference voltage. Channels C and D have a separate reference voltage, nominally also
3.3V, supplied by the LP3906 regulator designated as IC18. The reference voltage for
Channels C and D can be modified, as described in “I2C Voltage Adjustment Interface,”
page 138 .
The reference voltages themselves have a ± 5% tolerance, so there are slight corresponding
variances in the output voltage.
V OUT = --------------------- × V REFERENCE
D [ 11:0 ]
,
4096
Equation 10-1
UCF Location Constraints
Figure 10-5 provides the UCF constraints for the DAC interface, including the I/O pin
assignment and the I/O standard used.
NET
NET
NET
NET
"SPI_MOSI"
"SPI_SCK"
"DAC_CS"
"DAC_CLR"
LOC
LOC
LOC
LOC
=
=
=
=
"AB14"
"AA20"
"W7"
"AB13"
|
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
=
=
=
=
LVCMOS33 | SLEW
LVCMOS33 | SLEW
LVCMOS33 | SLEW
LVCMOS33 | SLEW
=
=
=
=
SLOW
SLOW
SLOW
SLOW
|
|
|
|
DRIVE
DRIVE
DRIVE
DRIVE
=
=
=
=
8
8
8
8
;
;
;
;
NET
"DAC_OUT"
LOC
=
"V7"
|
IOSTANDARD
=
LVCMOS33 ;
Figure 10-5:
UCF Location Constraints for the DAC Interface
Related Resources
Refer to the following links for additional information:
82
?
?
?
LTC2624 Quad DAC Data Sheet
h ttp://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1005,C1156,P2048,D2170
Xilinx PicoBlaze Soft Processor
http://www.xilinx.com/picoblaze
Digilent, Inc. Peripheral Modules
h ttp://www.digilentinc.com/Products/Catalog.cfm?Nav1=Products&Nav2=Peripheral&Cat=Peripheral
www.xilinx.com Spartan-3A/3AN FPGA Starter Kit Board User Guide
UG334 (v1.1) June 19, 2008
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