收藏本站
参数资料
型号： IDT88P8342BHGI
厂商： IDT, Integrated Device Technology Inc
文件页数： 56/98页
文件大小： 0K
描述： IC SPI3-SPI4 EXCHANGE 820-PBGA
标准包装： 24
系列： *
其它名称： 88P8342BHGI
6
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
List of Tables (Continued)
Table 57 - SPI-3 egress test register (register_offset=0x02) ............................................................................................................................................ 59
Table 58 - SPI-3 egress fill level register (register_offset=0x03) ...................................................................................................................................... 60
Table 59 - SPI-3 egress max fill level register (register_offset=0x04) .............................................................................................................................. 60
Table 60 - LID associated event counters (0x000-0x17F) .............................................................................................................................................. 61
Table 61 - Non LID associated event counters (0x00 - 0x0B) ........................................................................................................................................ 61
Table 62 - Non LID associated interrupt indication register (register_offset 0x0c) ............................................................................................................. 62
Table 63 - Non LID associated interrupt enable register(register_offset 0x0D) ................................................................................................................ 62
Table 64 - LID associated interrupt indication register (register_offset 0x0E) .................................................................................................................... 62
Table 65 - LID associated interrupt enable register (register_offset 0x0F) ....................................................................................................................... 62
Table 66 - Non critical LID associated capture table (register_offset 0x10-0x15) ............................................................................................................. 63
Table 67 - SPI-3 to SPI-4 critical LID interrupt indication registers (register_offset 0x16-0x17) ......................................................................................... 63
Table 68 - SPI-3 to SPI-4 critical LID interrupt enable registers (register_offset 0x18-0x19) ............................................................................................ 63
Table 69 - SPI-4 to SPI-3 critical LID interrupt indication registers (register_offset 0x1A-0x1B) ........................................................................................ 63
Table 70 - SPI-4 to SPI-3 critical LID interrupt enable registers (register_offset 0x1C-0x1D) ........................................................................................... 63
Table 71 - Critical events source indication register (register_offset 0x1E) ....................................................................................................................... 63
Table 72 - SPI-3 ingress packet length configuration register .......................................................................................................................................... 64
Table 73 - SPI-4 egress port descriptor table (64 entries) ............................................................................................................................................... 64
Table 74 - SPI-4 egress DIRECTION code assignment ................................................................................................................................................. 64
Table 75 - SPI-3 ingress port descriptor table (Block_base 0x1200) ............................................................................................................................... 64
Table 76 - SPI-3 to SPI-4 PFP register (register_offset 0x00) ......................................................................................................................................... 65
Table 77 - NR_LID field encoding .................................................................................................................................................................................. 65
Table 78 - SPI-3 to SPI-4 flow control register (register_offset 0x01) ............................................................................................................................... 65
Table 79 - SPI-4 ingress packet length configuration (64 entries configurable) ................................................................................................................ 66
Table 80 - SPI-3 egress port descriptor table (64 entries) .............................................................................................................................................. 66
Table 81 - SPI-3 egress DIRECTION code assignment ................................................................................................................................................. 66
Table 82 - SPI-4 ingress port descriptor tables (64 entries) ............................................................................................................................................ 66
Table 83 - SPI-4 to SPI-3 PFP register (0x00) ............................................................................................................................................................... 67
Table 84 - NR_LID field encoding .................................................................................................................................................................................. 67
Table 85 -Common Module (Module_base 0x8000) indirect register table ...................................................................................................................... 68
Table 86 - SPI-4 ingress LP to LID map (256 entries, one per LP) ................................................................................................................................. 69
Table 87 - SPI-4 ingress calendar_0 (256 entries) ......................................................................................................................................................... 69
Table 88 - SPI-4 ingress calendar_1 (256 entries) ......................................................................................................................................................... 69
Table 89 - SPI-4 ingress configuration register (0x00) .................................................................................................................................................... 69
Table 90 - SPI-4 ingress status configuration register (register_offset 0x01) .................................................................................................................... 70
Table 91 - SPI-4 ingress status register (register_offset 0x02) ........................................................................................................................................ 70
Table 92 - SPI-4 ingress inactive transfer port (register_offset 0x03) ............................................................................................................................... 70
Table 93 - SPI-4 ingress calendar configuration register (0x04 to 0x05) ......................................................................................................................... 71
Table 94 – SPI-4 ingress watermark register (register_offset 0x06) ............................................................................................................................... 71
Table 95 - SPI-4 ingress fill level register (0x07 to 0x08) ............................................................................................................................................... 71
Table 96 - SPI-4 ingress max fill level register (0x0B and 0x0C) ................................................................................................................................... 71
Table 97 - SPI-4 ingress diagnostics register (register_offset 0x0F) ................................................................................................................................ 71
Table 98 - SPI-4 ingress DIP-4 error counter (register_offset 0x10) .............................................................................................................................. 72
Table 99 - SPI-4 ingress bit alignment control register (register_offset 0x11) ................................................................................................................... 72
Table 100 - SPI-4 ingress start up training threshold register (register_offset 0x12) ........................................................................................................ 72
Table 101 - SPI-4 egress LID to LP map (128 entries) ................................................................................................................................................... 72
Table 102 - SPI-4 egress calendar_0 (256 locations) .................................................................................................................................................... 72
Table 103 - SPI-4 egress calendar_1 (256 locations) .................................................................................................................................................... 73
Table 104 – SPI-4 egress configuration register_0 (register_offset 0x00) ........................................................................................................................ 73
Table 105 - SPI-4 egress configuration register_1 (register_offset 0x01) ........................................................................................................................ 73
Table 106 - SPI-4 egress status register (register_offset 0x02) ....................................................................................................................................... 74
Table 107 - SPI-4 egress calendar configuration register (Register_offset 0x03 - 0x04) .................................................................................................. 74
Table 108 – SPI-4 egress diagnostics register (register_offset 0x05) .............................................................................................................................. 74
Table 109 - SPI-4 egress DIP-2 error counter (register_offset 0x06) ............................................................................................................................. 74
Table 110 - SPI-4 ingress bit alignment window register (register_offset 0x00) ................................................................................................................ 75
Table 111 - SPI-4 ingress lane measure register (register_offset 0x01) .......................................................................................................................... 75
相关PDF资料
PDF描述
LT1528CT IC REG LDO 3.3V/ADJ 3A TO220-5
RCE40DHFT CONN EDGECARD 80POS 1MM SMD
RBE40DHFT CONN EDGECARD 80POS 1MM SMD
MIC5295-3.0YD TR IC REG LDO 3V .15A TO-252-5
LT3015IMSE#TRPBF IC REG LDO NEG ADJ 1.5A 12MSOP
相关代理商/技术参数
参数描述
IDT88P8342BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装
IDT88P8344 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
IDT88P8344BHGI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装
IDT88P8344BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装
IDT89H10T4BG2ZBBC 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*